Panasonic FP-E - Page 558

High−level Instructions
3 − 294
Outline Inverts a specified bit in 16-bit data.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P132 (PBTI)” is are not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F132 BTI , DT 0 , DT 10
D
n
Trigger
R0
10
11
ST R 0
F132 (BTI)
DT 0
DT 10
D 16-bit area
n 16-bit equivalent constant or 16-bit area to specify bit position
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
IX
(*3)
IY
(*4)
K H
Index
modifier
D N/A A A A A A A A A A A N/A N/A A
n A A A A A A A A A A A A A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*4) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is ID.
Explanation of example
Inverts the state of bit specified by DT10 in data register DT0 when trigger R0 turns on.
When the DT10 = K7, as shown below.
00 00 01 01
·· ·
Bit position
·····
DT0
15
000
12
0
11
000
8
1
7
001
4
1
3
001
0
0
R0: on
·· ·
Bit position
·····
DT0
15
0
12
0
11
0
8
1
7
1
4
1
3
0
0
0
Condition of bit position 7 is inverted [off (0) → on (1)] when R0 turns on.
(Bits other than the specified bit are not changed.)
[D]
[D]
[n] DT10: K7
F132
P132
(PBTI)
(BTI)
16-bit data bit invert
A: Available
N/A: Not Available
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