Panasonic FP-E - Page 734

High−level Instructions
3 − 470
Outline When the elapsed value of the specified channel of the high−speed
counter matches the target value, the specified output is turned off.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F167 HC1R , K 0 , K −200 , Y0
Trigger
R0
D
DF
S
n
10
11
12
ST R 0
DF
F167 (HC1R)
K0
K − 200
Y0
n
The channel number of the high−speed counter that corresponds to the match
output (FP0/FP−e/FPΣ: H0 to H3, FP−X: H0 to HB).
S
The high−speed counter target value data or the starting address of the area
that contains the data.
D The output coil that is turned off when the values match (Yn n: 0 to 7)
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR SV EV DT
IX
(*1)
IY
(*2)
K H
Index
modifier
n N/A N/A N/A N/A N/A N/A N/A N/A A A N/A
S A A A A A A A N/A A A A
D N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
(*1) I0 to IC on FPΣ/FP−X/FP0R
(*2) ID on FPΣ/FP−X/FP0R
Explanation of example
Target value
−200
0
R0
Y0
Elapsed value
End of F167 control
(clear)
OFF when matches target value
High−speed counter
control flag varies
Target value match off
(with channel specification)
F167
(HC1R)
Availability
FP0/FP0R/FP−e/
FPΣ/FP−X
A: Available
N/A: Not Available
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