High−level Instructions
3 − 471
High−speed counter control flag varies
FP0, FPΣ, FP−e R903A
FP−X, FP0R R9110
(Refer to next page)
The number of the high−speed counter control flag varies depending on the channel used.
Regarding the channel number and control flag for each model, refer to the table on the next page.
Description
The number specified in “S” is set as the target value of the high−speed counter, and when the elapsed value
matches the target value, the specified output “Yn” turns off (by interrupt processing).
The target value setting and target value match output control are cleared when the elapsed value matches
the target value.
Specify a 32−bit data value for the target value “S” within the following range:
FP0/FP−eK−8,388,608 to K8,388,607
FPΣ/FP−X/FP0R K−2,147,483,648 to K2,147,483,647
The “S” value is stored in the target value area when the instruction is executed.
Possible specification range for “Yn”:
Devices specified for the match ON/OFF output
Type Device area
FP0/FP−e Y0 to Y7
FPΣ Y0 to Y7
FPΣ (V3.10 or more)/FP0R Y0 to Y1F
FP−X Y0 to Y29F
However, for the device that is not implemented, only the memory turns ON/OFF.
However, when the output that is not implemented is specified, only the WY memory is set/reset.
Precautions during programming
Set the high−speed counter by the system register before using this instruction.
The high−speed counter control flag turns on when the execution condition of the F167(HC1S) instruction
turns on and remains on until the target value match output turns off. During this time, an instruction to the
high−speed counter of the same channel (F166 through F173) cannot be executed.
Before the elapsed value matches the target value, the target value and target value match output setting are
not cleared even if a hardware reset is performed (the elapsed value is cleared to “0”).
A check for double output with OT instructions, KP instructions, and other applied instructions is not
performed on the output Y that is specified for target value match output.
To turn on the target value match output that was turned off with this instruction, reset using an SET instruction
or F0(MV) instruction, or use as a pair with an F166(HC1S) instruction.
If both the normal program and the interrupt program contain code for the same channel, make sure both are
not executed simultaneously.
The high−speed counter control flag also changes during scanning.
The interupt program is able to be excuted, when the high−speed counter elapsed value equals the set target
value.
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