High−level Instructions
3 − 569
Outline The filter processing is executed for the specified bits and the bitwise
results are output.
Program example
Boolean
Ladder Diagram
Address Instruction
10
F182 FILTR, WX0, DT 1, DT2, WR10
S1
Trigger
R0
S3
S2
D
10
11
ST R 0
F182 (FILTR)
WX 0
DT 1
DT 2
WR 10
S1 16−bit area for storing object data for filter processing
S2 16−bit equivalent constant or 16−bit area for storing object bits for filter
processing
S3 16−bit equivalent constant or 16−bit area for storing filter processing time
D 16−bit area for storing filter processing results
Operands
Relay Timer/Counter Register
Index
register
Operand
WX WY WR WL SV EV DT LD
In
(*1)
SWR SDT
K H
modifier
S1 A A A A A A A A A A A N/A N/A N/A
S2 A A A A A A A A A A A A A N/A
S3 A A A A A A A A A A A A A N/A
N N/A A A A A A A A A N/A N/A N/A N/A N/A
(*1) I0 to ID
Operation
In the 16−bit data stored in the area specified by S1, the bits of 0 specified by S2 are output directly, and the
bits of 1 are output by performing the filter processing for the time specified by S3 (0 to 30000 in msec unit).
The results are stored in the area specified by D in bit unit. (The bit positions are the same as S1.)
The bit position of S1 and D corresponds
respectively.
FP–e
Time constant processing
F182
(FILTR)
Availability
FP−X V2.0 or more
FPΣ V3.10 or more
FP0R
A: Available
N/A: Not Available
Phone: 800.894.0412 - Fax: 888.723.4773 - Web: www.clrwtr.com - Email: info@clrwtr.com
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