Panasonic KX-TG1032S

84
KX-TG1032S/KX-TG1033S/KX-TG1034S/KX-TGA101S
14.2. CPU Data (Handset)
14.2.1. IC1 (BBIC)
Pin No. Description I/O Connection at Normal mode at Reset mode
1 INT1n/P1[1] D,I ROW1 I I-PU
2 VDDIO S VDDIO S -
3 VDD S VDD S -
4VSS S VSS S -
5 LED1/PWM0/P2[0] D,O - O I-PU
6 LED2/PWM1/P2[1] D,O LCD_CSB O I-PU
7 LED3 A,I LCD_BACKLIGHT I I
8 LED_BIAS/P3[6]/PD6 A,O LED_BIAS O I-PD
9 SDA1/P2[5] D,IO LCD_SI O I
10 SCL1/P2[4] D,O LCD_SCL O I
11 INT5n/VDDE/P1[5] D,O LCD_RS O O-H
12 INT2n/P1[2] A,I ROW2 I I-PU
13 AVD S AVD S -
14 AVS S AVS S -
15 CAP A,I CAP I I
16 Xtal1 A,I Xtal1 I I
17 VSSRF S VSSRF S -
18 RFCLKp A,O - O O-HiZ
19 RSSI/RFCLKm I RSSI I O-HiZ
20 VDDRF S VDDRF S -
21 RFCLKd D,O RFCLK O O-H
22 TDO A,O TDO O O
23 RDI D,I RDI I I
24 SK D,IO SK O O-L
25 SIO D,IO SIO I I-PD
26 LE D,IO LE I O-H
27 P3[1]/PD1 D,IO COL1 I/O I-PD
28 P3[2]/PD2 D,IO COL2 I/O I-PD
29 VSSPA S VSSPA S -
30 PAOUTp A,O PAOUTp O I-PD
31 VDDPA S VDDPA S -
32 PAOUTp A,O PAOUTp O I-PD
33 VSSPA S VSSPA S -
34 P3[3]/PD3 D,IO COL3 I/O I-PD
35 P3[4]/PD4 D,IO COL4 I/O I-PD
36 TDOD/P3[5]/PD5 D,IO COL5 I/O I-PD
37 VSS S VSS S -
38 VDDIO S VDDIO S -
39 VDD S VDD S Å|
40 PCM_FSC/INT0n/P1[0] D,IO ROW0 I I-PU
41 P0[0]/UTX D,O UTX O I-PU
42 P0[1]/URX D,I URX I I-PU
43 P0[2]/JTIO D,IO JTAG Çh I-PU
44 P0[3]/SDA2 D,IO EEP_SDA I/O I-PU
45 P0[4]SCL2 D,IO EEP_SCL O I-PU
46 P0[5]/SPICLK/PCM_CLK D,O RINGER_LED O I-PU
47 P0[6]/SPIDO/PCM_DOUT D,O - O I-PU
48 P0[7]/SPIDI/PCM_DIN D,O RESET O I-PU
49 VSS S VSS S -
50 VDD S VDD S -
51 P2[3]/ADC1 D,O - O I
52 P1[7]/CHARGE/INT7 D,I CHARGE I I-PD
53 RSTn A,IO RSTn O I-PU
54 DC_stab A,O DC_stab O O
55 DC_I A,I DC_I I I
56 DC_CTRL D,O DC_CTRL O I-PU
57 DC_Sence A,I DC_Sence I I
58 VBAT1 A,I VBAT1 I I
59 LDO1_CTRL A,I LDO1_CTRL I I
60 LDO2_CTRL A,I LDO2_CTRL I I
61 P1[6]/PON/INT6 D,I POWER_KEY I I-PD
62 P2[6]/stop_charge A,O stop_charge O O-L