Panasonic TH 42PD50U - DT-Board Block Diagram

13.19. DT-Board Block Diagram
POWER_DET
SDBOOT
XRST
SBO1
SBI1
TCK
TMS
TDO
TDI
TRST
SCL1
SDA1
SDA_TV
SCL_TV
VIDEO_OUT
L_OUT
R_OUT
MAIN_SW
AFT
TMS
TCK
MPEG_DATA_EN
MPEG_CLK
MPEG_PKT_SYNC
SER_DATA
XFERST
POWER_DET
SD_BOOT
SBI1
SBO1
ADIN
PDWN
SLRCK
DL
R_OUT
DR
VIDEO_OUT
AFT
FAT_P
FAT_N
MPEG_CLK
SER_DATA
XFE_RST
TDI
MPEG_DATA_EN
MPEG_PKT_SYNC
TD_PEAKS
TCK
TMS
TRST
L_OUT
SDA_TV
SCL_TV
MAIN_SW
SDA_FE
SDA_FE
SCL_FE
SCL_FE
ADIN
PDWN
SLRCK
SCL1
SCL1
MAIN_R
MAIN_L
XRST
D_A_SW
D_A_SW
SDA1
SDA1
R_OUT
L_OUT
TD_PEAKS
X8005
X8200
58
41
36
35
37
43
R_OUT
MAIN_SW
TDO
SCL_TV
TCK
AFT(AFT1)
TDI
TRST
SCL1
SDA1
SDA_TV
TMS
L_OUT
MAIN_R
30
32
33
34
DT12
28
29
26
27
96
88
97
105
MVCLK0
MHSYNC0
MVSYNC0
20
VOUTENB
DC(BS_C)
45
47
DY(BS_Y)
23
POWER_DET
15
SDBOOT
16
XRST
22
SBO1(SBI1)
18
SBI1(SBO1)
19
30V(BT30V)
8
SUB 9V
51
52
SUB 9V
53
SUB 9V
54
SUB 5V
57
SUB 5V
IC8241
SD
1
HG
14
DC-DC CONV.3.3V
LG
7
2
FB
3.3V(1.8A)
10
SUB 5V
VCC
ISEN
12
BOOT
5
S1 G1
SUB 9V
D1
S2 G2 D2
SUB 5V
FDC_A5V
A5V
SUB 9V
MAIN_L
60
VIDEO_OUT
13
MVY0
MVY7
MVC0
MVC7
107
106
109
SRQ
24
RESET
VDD
IC8227
OUT
21
RESET
VDD
IC8228
VOUT
VDD
3
VOUT
AVR +2.5V
3.3V
IC8235
CE
16
+2.5V
SUB 9V
3.3V
XRST
30V
TO DG22
46
29
38
37
28
27
26
11
21
23
10
2
22
20
IC8230
BUS SWITCH
MVY7
MVY0
MVC7
MVC0
MHSYNC0
MVSYNC0
MVCLK0
IEC_OUT
MVY0
MVC0
MVY7
MVC7
47 48
Q8216
XSRQ
DY
DC
SDA1
SCL0
SDA0
SCL1
SCL0
SDA1
SDA0
SCL1
TD0
TCK
TDI
TMS
POWER_DET
SD_BOOT
XRST
TDO
SBO1
SBI1
SBO0
SBI0
+5V
SBI0
DT07
3
1
2
SBO0
SUB 5V
VDDQ
2.5V
(DDR SDRAM)
AVDDMVAVDDSVAVDDMAVDDDAVDDAAVDDVDD33VDD12
2.5V
DACRST
PDWN
SRCK
DACCK
LRCK
DMIX
CLK74
VC27
SD_DATA0
MMA13
SD_DATA2
SD_DATA1
MMA0
MCK27
SDCLK
SDWP
SDCMD
SDCD
SD_DATA3
1.2V 3.3V
PEAKS_Lite(2/3)
SLRCK
ADIN
HDSL PEAKS_Lite
IC8240
PDN
SDTI
LRCK
MCLK
4
2
3
5
1
BICK
10
11
AOUTL
AOUTR
IC8200
AUDIO DAC
OP AMP
IC8201
3
2
7
1
5
6
SUB 9V
1
2
3
4
9
10
11
13
5
6
12
8
IC8232
AUDIO INPUT SW(D/A)
256M DDR_SDRAM
IC8009,IC8010
128M WORK CPU SDRAM
IC8222
64M CPU FLASH ROM
IC8223
MMDQ0
MMDQ31
ED31
ED16
XEWE2
XECS0
EA22
EA1
DATA3
7
DATA0
8
DATA1
DATA2
9
1
2
CMD
5
CLK
WP
D_SW
DT09
VIN
9
11
133M
10
4
27M
7
24.576M
74M
X1
16
X2
1
IC8022
VCX0
AUDCLK
IC8203
CONT
2
L/H CHECK
O/I
4
I/0
1
Q8219
H
L
DIGITAL
ANALOG
D_A_SW
O/I
21
CONT
I/0
L/H CHECK
IC8204
4
AGC AMP
5
1
7
3
2
IC8205
6
4
2
8
6
9
12
1
3
5
SERIAL SW
10
11
13
IC8202
Q8217
Q8218
D_A_SW
AGC AMP(IF STRIP)
IC8206
3
2
4
7
6
OUT1
OUT2
AGC CTL
AGC AMP(IF STRIP)
7
4
2
IC8207
3
OUT2
AGC CTL
OUT1
6
39
40
35
36
62
63
53
54
87
88
134
133
136
135
68
137
94
106
108
91
RF_AGC
OBMSCL
XO
IF_AGC
OBMSDA
XI
FAT_P
FAT_N
SDA
TDO
SCL
TCK
TDI
NRST
TMS
TRST
MPEG_DATA
MPEG_CLK
MPEG_DATA_EN
MPEG_PKT_SYNC
IC8211
FRONT PROCESSOR(TERRESTRIAL RECEIVER)
5
IC8229
SDA
6
SCL
EEPROM
12
TU8200
VIDEO_OUT
L_OUT
15
R_OUT
11
8
9
SDA
16
AFT
TV TUNER
10
SCL
13
AGC
7
20
18
2
19
4
V_SUPPLY
BV
IF_SW
IF_OUT
BTL
ANT_V_SUPPLY
A5V
X9303P
XF8200
30V
FDC_CONT
176
X9351P
XF8201
H
IF_SW
L OFF
ON
H
OFF
ON
L
Q8220
H
L
DIGITAL
ANALOG
D_A_SW
16Bit AUDIO A/D
2
AINL
IC8244
LRCK
1
SDTO
13
9
AINR
10
PDN
(SW_OFF)
(SDA0B)
(SCL0B)
DT
H
STOP
OUT
L
Q8209
IF_SW
XERE
RE
CLE
ALE
XWP
WE
BOOT ROM I/F
PEAKS_Lite(3/3)
PEAKS_Lite(1/3)
JTAG I/F
3.3V
D8208
DIGITAL AUDIO OUT
CONTROL BUS(NAND I/F)
DATA B US
ADDRESS BUS
CONTROL BUS
Q8221
Q8222
IC8242
SD
1
HG
14
DC-DC CONV.1.2V
LG
7
2
FB
1.2V(1.5A)
10
SUB 5V
VCC
ISEN
12
BOOT
5
S1 G1
SUB 9V
D1
S2 G2 D2
SD CARD SLOT
DATA B US
ADDRESS BUS
CONTROL BUS
MAIN_SW
H
DIGITAL
ANALOG
L
XRST
ATSC INTERFACE
ENABLE0
PSYNC0
SCHDATA0
SCHCLK0
Test
Group
Joint
Action
JTAG
AGC OUT
ANALOG_R
ANALOG_L
XFE.RESET
TH-42PD50U
DT-Board Block Diagram
TH-42PD50U
DT-Board Block Diagram
TH-42PD50U
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