Panasonic TH-P54Z1D

46
10.4. Tuner box (2/3) Block Diagram
SUB1.8V
SUB3.3V
SUB_FS_3.3V
SUB3.3V
F15V
SUB5V
SUB_FS_1.8V
SUB3.3V
D5443
SUB1.8V
D5444
SUB1.2V
D5434
BT30V
D5431
D5432
STB3.3V
D5488
12V
SUB6V
SUB9V
Q5431
SUB5V
D5441
SUB6V
SUB3.3V
12V
SUB5V
D5498
D5500
D5433
D5449
D5442
D5499
Q5432
D5437
SUB9V
(MAIN MPU+VIDEO SIGNAL PROCESSOR)
RESET
ETHERNET
CONTROL
3.3V
IC8001
IIC3
3.3V
CPU BUS
I/F
IC8502
IC8580
IIC3
Peaks AVC
IC8581
1.2V
IC5470
BOOT
ROM
NAND
FLASH
DDR2
SBO2
DDR I/F
GC6 RST
RESET
IC8002,03
1.8V
IC8503
IIC0
GC3FS next
EEPROM
IC4001
IIC1
CLOCK
GEN
EEPROM
IC8004
CLOCK
LVDS DATA
IIC2
LVDS_I/F
ETHERNET
1.8V
IC5110
3.3V
IC4002
OSD_16bit
IC8504
LOSD_OUT
IECOUT
Y/UV_16bit
+1.8V
SBI2
IC4005
PCI BUS
I/F
DMIX0
JK8301
DAUDIO
+3.3V
LVDS RX
USB I/F
TUNER SOS
16
18
14
9
10
17
6
11
4
5
12
15
7
2
13
8
26
22
30
27
24
37
28
21
29
36
34
33
31
35
23
25
32
SUB1.2V
SUB1.8V
SUB3.3V
SUB5V
SUB9V
SUB6V
F15V
STB5V
STB3.3V
BT30V
SUB5V
SUB9V
STB5V
SUB6V
F15V
SUB3.3V
STB3.3V
12V
A DIGITAL SIGNAL PROCESSOR