User Manual For CYCLONE FX Programmers 87
9.2.2.9 Connection Related (MPC5xxx, SPC5xxx) Processors
9.2.2.9.1 :DEBUGFREQUENCY n
Processors: ARM, ColdFire, PPC, MAC7xxx, DSC, PPCNexus
Specifies the communications frequency with the target device.
n Frequency in Kilohertz.
9.2.2.9.2 :UNCENSOR n
Processors: PPCNexus
This parameter should be used if 64-bit and 256-bit censorship passwords are needed to bypass
security.
Note: The ASCII version of the password must have each long word separated by a dash.
n Password represented as a hexadecimal value, with no symbols or spaces
9.2.2.9.3 :RSTLOWPOSTSAP
Processors: All
Drives the RESET signal LOW before and after SAP operations.
9.2.2.10 Connection Related - DSC Processors
9.2.2.10.1 :DEVICE string
Processors: ARM, DSC, MAC7xxx
Describes the device being programmed.
string Describes the device being programmed.
9.2.2.10.2 :RSTLOWPOSTSAP
Processors: DSC, STM8
Drives the RESET signal LOW before and after SAP operations.
9.2.2.11 Connection Related - MON08 Processors
When using MON08 devices, the user must specify :POWERVOLTAGE and :POWERUPDELAY &
:POWERDOWNDELAY.
9.2.2.11.1 :DEVICECLOCK n
For Class 5, 6, 7, and 8 devices. Controls whether the Cyclone should drive a clock to the target or
whether the PEmicro interface should tristate its clock output. Valid values of n are:
0 : Clock driven by Cyclone. Must use :OUTPUTCLOCK to specify.
1 : Target self-clocked, Cyclone clock output disabled
9.2.2.11.2 :OUTPUTCLOCK n
Specifies the clock when :DEVICECLOCK is set to 0 (driven by Cyclone). Valid values of n are:
0 : 4.9152 MHz
1 : 9.8304 MHz
9.2.2.11.3 :CLOCKDIVIDER n
For Class 5, 6, 7, and 8 devices. Often one of the port pins of the target processor controls the
ratio of the BUS clock to the External clock. Valid values of n are:
0 : Divide by 2 (usually and if applicable)
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