Philips L9.2A - Circuit Descriptions - Tuner, IF, and Video Processing; Tuner Pin Descriptions and Functionality; IF Filter and Video IF Stages; IF Amplifier, PLL, Video Buffer, AGC, AFC

Circuit description new circuits
GB 59L9.2A 9.
9.5.2 Tuner
The PLL tuner (item 1000) is digitally controlled via the I2C-
bus. The tuner is suitable to receive off-air, S-(cable) and hyper
band channels.
Tuner pin description:
• Pin 1: AGC, Automatic gain control voltage input (0.3 -
4.0V)
• Pin 2: VT, tuning voltage input (not connected)
• Pin 3: AS, address select (not connected)
• Pin 4: SCL, IIC-bus serial clock
• Pin 5: SDA, IIC-bus serial data
• Pin 6: not connected
• Pin 7: Vs, PLL supply voltage +5V
• Pin 8: not connected
• Pin 9: Vst, tuning voltage +33V
• Pin 10: ground
• Pin 11: IF, asymmetrical IF output
Note: The +5V supply voltage and the +33V tuning voltage is
derived from the line output stage, see diagram A2).
9.5.3 IF band pass filter (SAW FILTER)
Between the tuner output and the video IF input of the video
processor the IF band pass filtering take place. Filter 5002 is
tuned at 40.4MHz and serves as an extra suppression of the
neighbour channel. For the IF band pass filtering SAW filters
are used (item 1003 or 1004). 5 Types of SAW filters are used
depending of the version of the set.
9.5.4 Video IF
General: Video IF-demodulation is achieved in combination
with reference circuit L5006 connected at pin 3 and 4 of
IC7250-A. The AGC control for the tuner is applied via pin 54
of IC7250-A. Internally the IC uses the top sync level as a
reference for AGC control. The AGC adjustment can be
readjusted via the SAM (service alignment menu). C2201
connected to pin 53 determines the time constant of the AGC.
The Base band CVBS signal is present at pin 6 of IC7250-A
(normal amplitude 3.2Vpp). From here the signal is fed via
transistor 7266 to the sound trap filters and then on to the video
source selection circuit.
The main functions of the video IF part are (see also figure 9.5):
• IF- amplifier
• PLL-demodulator
• Video buffer
•AFC
• IF-AGC
• Tuner AGC
9.5.5 IF- amplifier
The IF-amplifier incorporates symmetrical inputs (pins 48 and
49). By using IIC bus control (IFS) the AGC attenuation can be
adjusted by up to -20db.
Remark: If the BIMOS is replaced the AGC value should be
adjusted as part of the repair process. (see software alignment
adjustments).
9.5.6 PLL-demodulator
The IF-signal is demodulated with the assistance of the PLL
detector. The video IF-demodulator can handle both negative
and positively modulated IF signals; selection is achieved via
the IIC bus (bit MOD).
9.5.7 Video buffer
The video buffer is present to provide a low ohmic video output
with the required signal amplitude. Additionally, it provides
protection against (pin 6) the occurrence of noise peaks. The
video buffer stage also contains a level shifter and a gain stage
for both the positive and negative video modulation formats, so
that the correct video amplitude and DC level are always
present at pin 6 regardless of the input signal.
9.5.8 Video-IF AGC
An AGC system controls the gain of the IF amplifier such that
the video output amplitude is constant. The demodulated video
signal is supplied, via a low pass filter inside the IC to an AGC
detector. External AGC de coupling is provided by capacitor
2201 at pin 53. The AGC detector voltage directly controls the
IF amplification stages.
9.5.9 The tuner AGC
Tuner AGC is provided to reduce the tuner gain and thus the
tuner output voltage when receiving to strong RF signal. The
tuner AGC starts working when the video-IF input reaches a
certain input level. This level can be adjusted via the IIC bus.
The tuner AGC signal is applied to the tuner via the open
collector output pin 54 of the BIMOS.
9.5.10 AFC
The AFC output information is available for search tuning. The
AFC output is available via the I2C bus ( AFA and AFB signals).
For alignment purposes it is displayed in the TUNER submenu
of the SAM (See chapter 8).
Figure 9-13 “BIMOS”
9.6 Video Signal Processing (see circuit diagram
A6)
9.6.1 Introduction:
The video signal processing can be divided in the following
parts:
• CVBS/Y/C input selection
• Luminance and chrominance signal processing
• PAL/NTSC and SECAM demodulation /Auto system
manager
• YUV/RGB processing/ black stretcher
• Second RGB insertion
• RGB processing
• Black current calibration loop
• Beaming current limiting
Above mentioned processing circuits are integrated in the TV-
processor (parts B and C). The surrounding components are
for the adaptation of the selected application. The I2C bus is
used for defining and controlling the signals.