Philips LC4.2E - 9.8 Video: Pixel Plus Part

Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 69LC4.2E AA 9.
Figure 9-3 Block diagram Scaler Part
9.7.1 Features
The Scaler provides several key IC functions:
• Scaling.
• Auto-configuration/ Auto-Detection.
• Various Input Ports:
– Analog RGB.
– DVI Compliant.
– Video Graphics.
• Integrated LVDS Transmitter.
• On-chip Micro-controller
9.7.2 Inputs
Analog RGB
The RGB input is fed to pins B2, C2 and D2. This input consists
of either the Hercules RGB output or the RGB/YpbPr input of
the VGA connector. The Scaler can switch between the two
signals via the PC_HD_SEL signal and selection IC SM5301.
PC (VGA) input
The VGA input is processed by the VGA block of the Scaler.
The Scaler supports pixel frequencies up to 165MHz.
YpbPr format is also supported via the VGA interface and
covers a resolution of 480p/560p/720p/1080i.
DVI-D input
The DVI-D input is processed by the Scaler and supports DVI
sources with a pixel clock frequency up to 81MHz.
9.7.3 Output
The Display Output Port provides data and control signals that
permit the Scaler to connect to a variety of display devices
using a TTL or LVDS interface. The output interface is
configurable for single or dual wide TTL/LVDS in 18, 24 or 30-
bit RGB pixels format. All display data and timing signals are
synchronous with the DCLK output clock. The integrated LVDS
transmitter is programmable to allow the data and control
signals to be mapped into any sequence depending on the
specified receiver format.
9.8 Video: Pixel Plus Part (diagram PP1 to PP4)
The Pixel Plus functionality is completely handled by an
Electronic Programmable Logic Device, EPLD (item 7101 on
diagram PP1, PP3). The LVDS output from the TV & Scaler
Board is fed trough a LVDS receiver (item 7201 on diagram
PP2) and then delivered to the EPLD. The EPLD processes the
signal and it is fed to the LCD panel via a LVDS transmitter
(item 7403 on diagram PP3).
The EPLD takes care of all picture improvement processing,
like:
• Colour improvement
– Blue stretch
– Green enhancement
– Saturation control
• Sharpness enhancement
– Non-linear horizontal peaking
– Non-linear vertical peaking
– Coring, clipping
ADDRESS
DDR
FRAME
STORE
INTERFACE
EXT.
FLASH
ROM
INTER-
FAC E
DISPLAY
TIMING
GEN
DVI
INPUT
PORT
ANALOG
INPUT
PORT
1
5
11
15
PC-IN
9
7
6
2
1
17
18
15
14
3,11,19,22
10
24
23
DDC
NVM
7693
6
5
8
DDC_5V
RXC+IN
RXC-IN
RX1+IN
RX0+IN
DVI-IN
16
HOT_PLUG
+5VSWI
3682
6692
6691
5692
3691
DDC_5V
3710
RX1-IN
SDA_DVI
SCL_DVI
DVI
NVM
7694
8
6
RX2+IN
RX2-IN
RX0-IN
u-Processor
HERCULES
IC
7011
FLASH
ROM
1,2
3,4,5
7
8
10,11
12
20
17
1403
TO LCD PANEL (LVDS)
6
9
14
15
13,16
18
19
TXB0-
TXBC+
TXB3+
TXB1-
TXB1+
TXBC-
TXB2-
TXB2+
TXB0+
TXB3-
SDRAM
DATA
DATA
GRAPHIC
ZOOM
VIDEO
ZOOM
OSD CONTROLLER
OUT BLENDER
BRIGHTNESS/CONTRAST/HUE/SAT
INTERNAL
ROM &
RAM
UART
INTERFACE
MICRO-
CONTROLLER
80186
HOT_PLUG
87
86
85
PA N_ V C C
7530
A10
7501
7401
GM1501
SXGA DISPLAY
CONTROLLER
GPIO_G07_B7
2488
1401
TCLK
XTAL
2487
+3V3_PLL
TO EPLD PANEL (PIXEL +)
6693 5686
DDC_5V
ADDRESS
VS
HS
PC_HD_DET+
RED_PR
GRN_Y
BLU_PB
7606
9, 17, 19
14
12
1
15
11
2
PC_HD_SEL
A 7
PC_HD_DET-
11 10
6604
6605
7604-5
PC_HD_DET
A7
7605
H_CS_SDTV
V_SDTV
VS
HS
SD_HD_SEL
7604
1
23 4
13 12
5
69 8
13
12
1
3
14
15
9,11
HD_FILTER
7604-6
7607
R_PR+
G_Y+
B_PB+
9
17
14
11
R_SDTV
G_SDTV
B_SDTV
RED_PR
GRN_Y
BLU_PB
H_CS
V
27
2
7
25
1
5
21
A2
A2
A2
A7
A2
A2
A7
SOG
SD_HD_SELA7
22
PC_HD_SEL
107
107
R_SDTV
G_SDTV
B_SDTV
H_CS_SDTV
V_SDTV
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