Quantum Q280

Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Table 5-1: Test Connector J5 Signals
Signal
Name
CAGC
BURST PEAK
SET HYST
DET REF
-WEDGE
GND
5 Vdc
12 Vdc
12 Vdc
5 Vdc
GND
N/C
+ENCODED
DATA
+DATA LOCK
N/C
+TEST
RD CLOCK
Description
AGC voltage for U2 (B). See section
2.3.5 and section 2.3.7.
See AMC Circuit in section 5.5.2, and
Figure 5-3.
1.2 V dc. This voltage is changed in
factory test to check the drive's
margin.
0.2 V dc. This voltage is changed in
factory test to check the drive's
margin.
See RDX, RDY, and -WEDGE in section
5.5.2, and Figure 5-2.
Same as +RAW DATA. See Figure 5-1.
TTL Level. Asserted by DICEY at end of
sync pattern check.
Same as +RD CLOCK. See Figure 2-13.
5-5