LTE Standard Module Series
EC21_Series_Hardware_Design
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Figure 7: Power Supply Limits during Burst Transmission
To decrease voltage-drop, use bypass capacitors of at least 100 µF with low ESR, and reserve a multi-
layer ceramic chip capacitor (MLCC) array due to their low ESR. It is recommended to use at least three
ceramic capacitors (100 nF, 33 pF, 10 pF) for composing the MLCC array, and place these capacitors
close to VBAT_BB and VBAT_RF pins. The main power supply from an external application has to be a
single voltage source and can be expanded to two sub paths with star structure. The width of VBAT_BB
trace should be no less than 1 mm; and the width of VBAT_RF trace should be no less than 2 mm. In
principle, the longer the VBAT trace is, the wider it will be.
In addition, in order to avoid the damage caused by electric surge and ESD, it is suggested that a TVS
diode with suggested low reverse stand-off voltage V
RWM
4.5 V, low clamping voltage V
C
and high reverse
peak pulse current I
PP
should be used. The following figure shows the star structure of the power supply.
Figure 8: Star Structure of the Power Supply
3.6.3. Reference Design for Power Supply
The performance of the module largely depends on the power source. The power supply should be able
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