LTE Standard Module Series
EC21_Series_Hardware_Design
56
/ 118
Table 14: Pin Definition of PCM and I2C Interfaces
Pin Name Pin No. I/O Description Comment
PCM_IN 24 DI PCM data input
1.8 V power domain
If unused, keep them open.
PCM_OUT 25 DO PCM data output
PCM_SYNC 26 DIO PCM data frame sync
1.8 V power domain.
Serve as output signal in master
mode.
Serve as input signal in slave mode.
If unused, keep them open.
PCM_CLK 27 DIO PCM clock
I2C_SCL 41 OD
I2C serial clock (for external
codec)
An external 1.8 V pull-up resistor is
required.
If unused, keep them open.
I2C_SDA 42 OD
I2C serial data (for external
codec)
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See document [2]
for more details about AT+QDAI.
The following figure shows a reference design of PCM and I2C interfaces with external codec IC.
Figure 24: Reference Circuit of PCM and I2C Application with Audio Codec
1. It is recommended to reserve an RC (R = 22 Ω, C = 22 pF) circuits on the PCM lines, especially for
PCM_CLK.
2. EC21 series only works as a master device pertaining to I2C interface.
NOTE
To Next Page
Loading...
Need help?
General
