It
acts somewhat like a
multipole,
multiposition
switch. When the Video Divider Chain
is
in con-
trol,
the
MUX
is
switched
so
that
only
addresses
from
the divider chain
are
directed
to
the Video
RAM. The
CPU
may
need
to
read
or
write
data
into
the Video RAM.
If
so,
the
MUX
is
switched
so
that
the
CPU
has
control
over Video RAM's
address.
After
the
CPU
is
finished, the address-
ing task
is
reassigned
to
the Divider Chain.
12
The
Memory
Map
Maybe you've asked the question
"Which
output
port
is
the display?" The answer
is
that
the TRS-
80 does
not
use
an
output
port
for
the display.
The TRS-80
is
memory-mapped. In a memory-
mapped system
an
address
will
define and select
all
other
subsections.
Figure
2 shows
the
Memory
Map
for
a Level I
TRS-80. From
memory
locations
0000
to
0FFF,
the Level I ROMs
are
present. The Keyboard
is
located
from
address
3800
to
38FF.
The Video
Display
is
located
from
3C00
to
3FFF.
The
RAMs start at
4000
and, depending on
how
much RAM
is
in the system,
can
extend
down
to
address
7FFF.
As
we
told
you before, upon power-on,
an
address location
is
outputted
by
the
CPU
re-
questing
information
from
the ROMs. Since the
ROMs
are
located at addresses
0000
to
0FFF,
the
CPU
will
be
outputting
addresses in this
area.
If
the
CPU
needs
some
kind
of
keyboard
data,
it
will
output
addresses
3800
through
38F F and
see
if
anything
is
in this
"memory"
location.
If
the
CPU
wants
to
show the pro-
grammer something on the display, all
it
has
to
do
is
address the Video Display section
of
the
map and store data in these locations. Some-
thing
to
remember: the Video Display shows
what
is
in
memory
locations 3C00 through
3FFF.
Notice
memory
locations 4000
to
41
F
F.
At
address
4000
RAM starts. But, part
of
the RAMs
are
used
by
BASIC
as
general housekeeping
memory locations. Hence, the user accessible
RAM actually starts at address
4200.
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