Radio Shack Quick Printer II Reference Handbook

RAM Addressing
In about the middle of Sheet 1, on the left side
of the RAM array, multiplexers Z35 and Z51 are
shown. On the left side of Z35, we find the area
where
four address lines are coming in. One
brace
of four is labeled "0" and the other is
labeled "1". Z51 is configured the same way
except there are only three lines per brace. The
otells us that when the select pin is low, the
multiplexer will be outputting data associated
with these input lines. The "1" tells us the oppo-
site is true. When the select pin on the multi-
plexer goes high, it will be
outputting data
associated with the "1" input address lines. The
select input for both multiplexers is pin 1. Z35.
therefore, operates somewhat like a 4-pole,
double throw switch, where the select input (pin
1)
is doing the switching. Z51 is used only as a
3-pole,
double throw switch - one input/output
is not used. The enable input to the multiplexer
is pin 15. Since pin 15 is grounded on both IC's,
the "switches" are always enabled.
Reading From RAM
Assume the CPU needs RAM data. Let's follow
the addressing and data paths the RAM will use.
We'll use a 4K RAM example.
The CPU outputs a MREQ and a RD. The
address decoder outputs MEM* and RAM*.
MEM* activates
the RAM/ROM data buffers and
RAM* enables
the chip enable (CEI for the
RAMs. At the same time, the multiplexer will
load
the address into the RAMs. RAS* goes low.
The MUX signal is low at this time, so Ar/J
through A5 on the RAM receive the low order
address. Notice that RAS* is buffered by Z68,
pins 14 and 13, and is applied to pin 4 of all the
RAMs. The negative going signal at pin 4 will
load
the lower order address in the row section
of each RAM. A short time later, MUX changes
state; it goes high. The multiplexer, Z35 and
Z51, now switch and the high order addresses
26
are applied to the RAMs. CAS* will now go low.
CAS*
is applied to buffer Z67, pin 14. Pin 13 of
Z67 passes CAS* to pin 15 of all eight RAMs.
On
the negative transition of CAS*, the high
order addresses (A6 through A11) will be loaded
in
the column section of each RAM. The RAMs
now have the entire address from the CPU. The
RAM will now output data through the buffers
and to the CPU.
Writing To RAM
The difference between a write operation and a
read operation is exactly two signals. Address
decoding
and address multiplexing work the
same way. During a data write, however, the
CPU sends data to the RAMs. Thus, the ROM/
RAM buffers are not needed; and MEM* will
not go low. Instead of the CPU issuing a RD
command, it supplies a WR instruction. WR* is
tied to all eight RAMs on pin 3. When this pin is
low, data will be stored in RAM at the specified
address. When this pin
is high, the RAMs are in
read cycle.
Refreshing the RAMs
The TRS-80 uses dynamic type RAM. A
dynamic RAM differs slightly from a static RAM
in data retention. A static RAM will retain data
stored in it as long as power is applied to it. A
dynamic RAM must be periodically addressed to
ensure that it retains the data loaded into it. The
periodic addressing is called "refreshing." You
might compare a dynamic RAM with an air-
filled tire with a slow leak. Every
once in a
while,
the tire must be shot a little air so it
won't go flat. If we don't service that tire, it
would finally become unusable. The same is true
of dynamic RAM. If the system does not access
the RAMs every so often, they will "forget"
data.
The dynamic RAM in the TRS-80 uses an
"RAS only" type of refresh. In other words,
when RAS* goes low,
the RAMs in the system
will
"refresh themselves" even though the RAM
may not be in use at the time. As stated before
,

Radio Shack Quick Printer II Specifications

General

Brand	Radio Shack
Model	Quick Printer II
Category	Desktop
Language	English