INSIG*
Exactly
how
the
CPU
turns
a string
of
ones
and
zeroes
into
the
text
of
a BASIC
program
would
interest
only
the
hardcore
software
person.
The
amount
of
hardware
used in
the
TRS-80
to
get
cassette
data
to
the
CPU
is
minimal.
Only
the
hardware
will
be
discussed.
Z25, pin 4,
is
tied
to
IN*. This signal will go low
when
the
CPU
wants
to
input
data
from
a
port.
Port
Addressing has
already
been discussed. A
low
at
pin 4
of
Z25
and
a low
at
address
decoder
Z36, pin 3, will
cause
a
jaw
at
Z25, pin 6, I
N-
SIG*. This signal
is
controlling
only
one
device
-
part
of
244. 244, pin 12,
is
tied
to
pin 8
of
NAND gate Z24.
The
two
NAND gates
of
Z24
are
wired
to
form
a set-reset latch. If pin 9 goes
low, pin 8 will go high. Pin 8
is
cross
tied
to
pin
12.
If
pin 13
is
high
and
since 12
is
high, pin
11
will
be
low. With a high
at
pin 8
and
a low
at
pin
11,
the
flip-flop
is
"set".
If pin 8
is
low
and
pin
11
is
high,
the
flip-flop
is
"reset".
The
flip-flop
is
being
set
by
cassette
data
and
reset by OUT-
SIG*.
Z44
monitors
the
status
of
Z24
under
command
from
INSIG*.
Here
is
how
it
works
during
a CLOAD
function:
When CLOAD
is
entered
via
the
Keyboard,
OUTSIG*
will go low,
starting
the
Recorder's
motor
and
resetting
224
by
pulsing pin 13 low.
The
first
time
Z24, pin 9 goes low.
the
first
bit
50
time
starts.
This
is
shown
in Figure 12
at
Line A.
Line
D,
the
output
of
the
latch, goes high as
soon
as pin 9 goes low.
OUTSIG*
goes low
after
a
short
time
delay,
shown
on
Line
C.
The
signal
will reset -the flip-flop as Line D shows. A
short
time
after
OUTSIG*
goes back high,
the
CPU
will
test
224,
pin
8's
status
by
enabling
244.
Line D
is
low
at
this
time.
The
CPU recognizes a
logical
"0"
during
bit
time
1 as
shown
by
the
0
under
Line
D.
The
next
time
Line A goes low
is
the
start
of
bit
time
2.
The
Iowan
Z24, pin
9,
sets
the
flip-flop. OUTSIG* resets
the
flip-flop
a
short
time
later. INSIG*
then
enables Z44
and
checks
the
status
of
the
flip-flop.
The
CPU
"sees"
a
zero
again,
so
bit
time
2
is
a
zero
bit.
The
next
low
on
line A
starts
bit
time
3.
It sets
the
flip-flop,
and
a
short
time
later
OUTSIG*
resets
the
flip-flop. Before INSIG* can
test
status,
another
low
comes
from
the
audio
pro-
cessing level
detector
and
sets
the
flip-flop.
Now
INSIG* goes low,
checking
status.
It finds
Z24,
pin 8. high.
The
CPU labels
bit
time
3 a "1
".
Now
the
CPU
must
reset
the
flip-flop
before
bit
time
4 starts. Line C
shows
the
added
OUTSIG*
pulse
to
reset Z24.
The
flip-flop
is
reset
and
stays
reset until
the
next
Iowan
Line A sets it
again.
The
CPU finds
bit
time
4
to
contain
a
zero.
This
set/reset
process
continues
until
the
CPU has read every
bit-time
of
the
program
that
was
stored
in
the
cassette. It
is
the
CPU's respon-
sibility
to
assemble
the
bit
times
into
data
words
the
words
into
text.
and
store
the
text
in,
RAM.
The
CPU
is
quite
busy
during
a CLOAD
function.
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