Radio Shack TRS-80 Model 4 Technical Reference Manual

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Name:
WRINTMASKREG*
Port Address:
0E0H
Access:
WRITE ONLY
Bit 7 = Undefined
Bit 6 = ENERRORINT; 1 enables RS-232 interrupts
on parity error, framing error, or data overrun
error.
0 disables above.
Bit 5 = ENRCVINT; 1 enables RS-232 receive data
register full interrupts,
0 disables above.
Bit 4 = ENXMITINT; 1 enables RS-232 transmitter
holding register empty interrupts,
0 disables above.
Bit 3 = ENIOBUSINT; 1 enables I/O Bus interrupts,
0 disables the above.
Bit 2 = ENRTC; 1 enables real time clock interrupt,
0 disables above.
Bit 1 = ENCASINTF; 1 enables 1500 Baud falling
edge interrupt,
0 disables above.
Bit 0 = ENCASINTR; 1 enables 1500 Baud rising
edge interrupt,
0 disables above.
Name:
CAS IN*
Port Address:
0FFH
Access:
READ ONLY
Bit 7 = 500 Baud Cassette bit
Bit 6 = Undefined
Bits = DISWAIT (See Port 0ECH definition)
Bit 4 = ENEXTIO (See Port 0ECH definition)
Bit 3 = ENALTSET (See Port 0ECH definition)
Bit 2 = MODSEL (See Port 0ECH definition)
Bit 1 = CASMOTORON (See Port 0ECH definition)
Bit 0 = 1500 Baud Cassette bit
NOTE:
Reading Port 0FFH clears the 1500 Baud
Cassette interrupts.
Name:
DRVSEL*
Port Address:
0F4H
Access:
WRITE ONLY
Bit 7 = FM*/MFM; 0 selects single density,
1 selects double density.
Bit 6 = WSGEN; 0 = no wait states generated,
1 = wait states generated.
Bit 5 = PRECOMP; 0 = no write precompensation,
1 = write precompensation enabled.
Bit 4 = SDSEL; 0 selects side 0 of diskette,
1 selects side 1 of diskette.
Bit 3 = Drive select 4
Bit 2 = Drive select 3
Bit 1 = Drive select 2
Bit 0 = Drive select 1

Radio Shack TRS-80 Model 4 Specifications

General

Brand	Radio Shack
Model	TRS-80 Model 4
Category	Desktop
Language	English