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4.2.9 Clock and Read Data Recovery Logic
The Clock and Read Data Recovery Logic is
comprised of one chip, the FDC9216. The FDC9216
is a Floppy Disk Data Separator (FDDS) which
converts a single stream of pulses from the disk drive
into separate clock and data pulses for input to the
FDC chip. The FDDS consists of a clock divider, a
long-term timing corrector, a short-term timing
corrector, and reclocking circuitry. The reference
clock (REFGLK) is 4 MHz and is divided by the
internal clock divider. CD0 and CD1 of the FDDS chip
control the divisor which divides REFCLK. With CD1
grounded (logic low), CD0 (when a logic low)
generates a divide-by-1 for MFM mode and when
logic high generates a divide-by-2 for FM mode. CD0
is controlled by the signal DDEN* which is Double
Density Enable or MFM enable. The FDDS detects
the leading edges of RD* pulses and adjusts the
phase of the internal clock to generate the separated
clock (SEPCLK) to the FDC chip. The separate long
and short term timing correctors assure the clock
separation to be accurate. The separated Data
(SEPD*) is used as the RDD* input to the FDC chip.
4.2.10 Floppy Disk Controller Chip
The 1793 is an MOS LSI device which performs the
functions of a floppy disk formatter/controller in a
single chip implementation. The 1793 is functionally
identical to the 1791 used on the Model II FDC
Printer Interface Board except that the data bus is
true as opposed to inverted. Refer to the appendix
section for more information on the FD1793. The
Model II Technical Reference Manual also contains a
good presentation of the 1791 FDC chip as well as a
discussion on Write precompensation. The following
port addresses are assigned to the internal registers
of the 1793 FDC chip:
Port # Function
F0H Command/Status Register
F1H Track Register
F2H Sector Register
F3H Data Register
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