Radio Shack TRS-80 Model 4 Technical Reference Manual

55
FLOPPY DISK INTERFACE
4.1 Model 4 FDC PCB #8858060
The TRS-80 Model 4 Floppy Disk interface Board is
an optional board which if incorporated provides a
standard five inch floppy disk controller. The Floppy
Disk Interface Board supports both single and double
density encoding schemes. This feature, along with a
special software package, allows the transfer of
Model I disk files to the Model 4 system. Write
precompensation can be software enabled or
disabled beginning at any track, although the system
software enables write precompensation for all tracks
greater than twenty-one. The amount of write
precompensation is continuously variable from 0
nsec to more than 500 nsec. The write pre-
compensation is factory adjusted to 200 nsec. The
data clock recovery logic incorporates a phaselocked
loop oscillator Which achieves state-of-the-art
reliability. One to four drives may be controlled by the
interface (two internal drives and two external). All
data transfers are accomplished by CPU data
requests. In double density operation, data transfers
are synchronized to the CPU by forcing a wait to the
CPU and clearing the wait by a data request from the
FDC chip. The end of the data transfer is indicated by
generating a non-maskable interrupt from the
interrupt request output of the FDC chip. A hardware
watchdog timer insures that error conditions will not
hang the wait line to the CPU for a period long
enough to destroy RAM contents.
4.1.1 Control and Data Buffering
Refer to the Schematic Diagram 8000095.
The Floppy Disk Controller Board is an I/O port
mapped device which utilizes ports E4H, F0H, F1H,
F2H, F3H, and F4H. The decoding logic is
implemented on the CPU board. (See the Decoding
Logic section of the CPU discussion.) U4 of the
Floppy Disk Controller Board is a non-inverting octal
buffer which isolates and buffers the required control
signals. Table 4-1 and Table 4-2 summarize the port
and bit allocation for the Floppy Controller Board. U2
of the Floppy Disk Controller Board is a bi-directional,
8-bit transceiver used to buffer data to and from the
Floppy Controller Board. The direction of data
transfer is controlled by the combination of control
signals DISKIN* and RDNMIMASKREG*. If either
signal is active (logic low), U2 is enabled to drive data
onto the CPU board data bus. If both signals are
inactive (logic high), U2 is enabled to receive data
from the CPU data bus.
4.1.2 Nonmaskable Interrupt Logic
A dual “D” flip-flop (U5) is used to latch data bits D6
and D7 on the rising edge of the control signal
WRNMIMASREG*. The outputs of US control the
conditions which will generate a non-maskable
interrupt to the CPU. The NMI-interrupt conditions are
programmed by doing an OUT instruction to port E4H
with the appropriate bits set. If data bit 7 is set, an
NMI will be generated by an FDC interrupt request. If
data bit 7 is reset, interrupt requests from the FOG
are disabled. If data bit 6 is set, an NMI will be gener-
ated by Motor Time Out. If data bit 6 is reset,
interrupts on Motor Time Out are disabled. An IN
instruction from port E4H enables the CPU to
question the Floppy Disk Controller Board to
determine the source of the non-maskable interrupt.
Data bit 7 indicates the status of FOG interrupt
request (0 = true, 1 = false). Data bit 6 indicates the
status of Motor Time Out (0 = true, 1 = false). Data bit
5 indicates the status of the front panel reset (0 =
true, 1 = false). The control signal
RDNMIMASKREG* when active (logic 0), gates this
status onto the CPU data bus.
4.1.3 Drive Select Latch and Motor On Logic
Selecting a drive prior to a disk I/O operation is
accomplished by doing an OUT instruction to port
F4H with the proper bit set. The following table
describes the bit allocation of the Drive Select Latch.
DATA BIT FUNCTION
D0 Selects Drive 0 when set *
D1 Selects Drive 1 when set *
D2 Selects Drive 2 when set *
D3 Selects Drive 3 when set *
D4 Side 0 selected when reset, side 1
selected if set
D5 Write Precom. engaged when set,
disabled if reset
D6 Generate waits if set, no waits if
reset
D7 Selects MFM mode if set, FM mode if
reset
*Only one of these bits should be set per output.
Table 4.1. Port F4H Bit Allocation
A hex “0” flip-flop (U6) latches the drive select bits,
side select and FM*/MFM bits on the rising edge of
the control signal IDRVSEL*. A dual “D” flip-flop
(U18) is used to latch the Wait Enable and
Precompensation enable bits on the rising edge of
IDRVSEL*. The rising edge of IDRVSEL* also
triggers a one-shot (1/2 of U15) which produces a
Motor On to the disk drives. The duration of the Motor
On signal is approximately two seconds. The spindle
motors are not designed for continuous operation,
therefore the inactive state of the Motor On signal is
used to clear the Drive Select Latch, which de-selects
any drives which were previously selected. The Motor
On one-shot is retriggerable by simply executing an
OUT instruction to the Drive Select Latch.

Radio Shack TRS-80 Model 4 Specifications

General

Brand	Radio Shack
Model	TRS-80 Model 4
Category	Desktop
Language	English