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perform this function. INTQ, DRQ, RESET, and
WAITIMOUT are the inputs to the NOR gate. If any
one of these inputs is active (logic high), the output of
the NOR gate (U9 pin 6) will go low. This output is
tied to the clear input of the wait latch. When this
signal goes low, it will clear the Q output (U18 pin 5)
and set the Q* output (U15 pin 6). This condition
causes WAIT* to go high which allows the Z-80 to
exit the wait state. U3 is a 12-bit binary counter which
serves as a watchdog timer to insure that a wait
condition will not persist long enough to destroy
dynamic RAM contents. The counter is clocked by a
1 MHz clock and is enabled to count when its reset
pin is low (U3 pin 11). A logic high on U3 pin 11
resets the counter outputs. U3 pin 15 is a divide-by-
1024 output and is used to generate the signal
WAITIMOUT. This watchdog timer logic will limit the
duration of a wait to 1024 µsec, even if the FDC chip
should fail to generate a DRQ or a INTRO.
4.2.5 Clock Generation Logic
A 4 MHz crystal oscillator and a 4-bit binary counter
are used to generate the clock signals required by
the FDC board. The 4 MHz oscillator is implemented
with two inverters (1/3 of U22) and a quartz crystal
(Y1). The output of the oscillator is inverted and
buffered by 1/6 of U22 to generate a TTL level
square wave signal. U21 is a 4-bit binary counter
which is divided into a divide-by-2 and a divide-by-8
section. The divide-by-2 section is used to generate
the 2MHz output at pin 12. The 2 MHz is NANDED
with a MHz by 1/4 of U17 and the output is used to
clock the divide-by-8 section of U21. A 1 MHz clock is
generated at pin 9 of U21 which is 90 degrees phase-
shifted from the 2 MHz clock. This phase relationship
is used to gate the guaranty Write Data Pulse (WD)
to the Write precompensation circuit. The 4 MHz is
used to clock the digital data separator U11 and the
Write precompensation shift register U10. The 1 MHz
clock is used to drive the clock input of the FDG chip
(U6) and the clock input of the watchdog timer (U3).
4.2.6 Disk Bus Selector Logic
As mentioned previously, the Floppy Disk Controller
board supports up to four drives (two internal and two
external). This function is implemented by using two
disk drive interface buses, one for the internal drives
and one for the external drives. J1 is the edge
connector used to drive the internal disk drives and
J4 is the edge connector used to drive the external
drives. U19 (a quad 2 to 1 data selector) is used to
select which set of inputs is routed from the disk drive
buses to the FDC chip. U19 pin 1 is the control pin for
the data selector. If pin 1 is low, the external inputs
are selected, otherwise the internal inputs are
selected. This control signal EXTSEL* is generated
from the outputs of the Drive Select Latch. If Drive 2
or 3 is selected, U20 pin 1 will go low indicating that
an external drive is selected. One half of U9 (a five-
input NOR gate) is used to detect when any of the
four drives is selected.
The output of the NOR gate (U9 pin 5) is inverted and
is used as the head load timing (HLT) and ready
(RDY) signal for the FDC chip. Therefore, if any drive
is selected, the head is assumed to be loaded and
the selected drive is assumed to be ready.
4.2.7 Disk Bus Output Drivers
High current open collector drivers (U18, U8, and U1)
are used to buffer the output signals from the FDC
board to the disk drives. Note from the schematic that
each output signal to the drives has two buffers
associated with each signal. One set is used for the
internal drive bus and the other set is used for the
external drive bus. No select logic is required for
these output signals since the drive select bits define
which drive is active.
4.2.8 Write Precompensation and Write Data
Pulse Shaping Logic
The Write Precompensation logic is comprised of
U10 (74LS195), 1/4 of U17, 1/4 of U20, and 1/2 of
U15. U10 is a parallel in, serial out shift register and
is clocked by 4 MHz which generates a
precompensation value of 250 nsec. The output
signals EARLY and LATE of the FDC chip (U6) are
input to P0 and P2 of the shift register. A third signal
is generated by 1/4 of U20 when neither EARLY nor
LATE is active low and is input to P1 of U10. WD of
the FDC chip is NANDed with 2 MHz to gate the
guaranteed Write Data Pulse to U10 for the parallel
load signal SHFT/LD. When U10 pin 9 is active low,
the signals preset at P1-P3 are clocked in on the
rising edge of the 4 MHz clock. After U10 pin 9 goes
high, the data is shifted out at a 250 nsec rate.
EARLY will generate a 250 nsec delay, NOT EARLY
AND NOT LATE will generate a 500 nsec delay, and
LATE will generate a 750 nsec delay. This provides
the necessary precompensation for the write data. As
mentioned previously, Write Precompensation is
enabled through software by an OUT to the Drive
Select Latch with bit 5 set. This sets the Q output of
the 74LS74 (U15 pin 9) which disables the shift
register U10. This signal also enables U20 to allow
the write data (WD) to bypass the Write
Precompensation circuit. The Write Date (WD) pulse
is shaped by a one-shot (1/2 of U3) which stretches
the data pulses to approximately 500 nsec.
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