Renesas RL78/G13 Operation

RL78/G13 Clock Generator (Clock Switching) CC-RL
R01AN2831EJ0100 Rev. 1.00 Page 27 of 51
May 28, 2015
Selecting clocks
 System clock control register (CKC)
: Select CPU/peripheral hardware clock (f
CLK
) status,
CPU/peripheral hardware clock (f
CLK
),
main system clock (f
MAIN
), and
control main system clock (f
MAIN
) operation.
Symbol: CKC
7 6 5 4 3210
CLSCSSMCSMCM00000
When HOCO clock is used 0 0 0 0 0000
When X1 oscillation clock is used 0 0 1 1 0000
When XT1 oscillation clock is used 1 1 0 0 0000
Bit 7
CLS
Note 1
Status of CPU/peripheral hardware clock (f
CLK
)
0 Main system clock (f
MAIN
)
1 Subsystem clock (f
SUB
)
Bit 6
CSS Selection of CPU/peripheral hardware clock (f
CLK
)
0 Main system clock (f
MAIN
)
1
Note2
Subsystem clock (f
SUB
)
Bit 5
MCS
Note 1
Status of main system clock (f
MAIN
)
0 High-speed on-chip oscillator clock (f
IH
)
1 High-speed system clock (f
MX
)
Bit 4
MCM0
Note 2
Main system clock (f
MAIN
) operation control
0
Selects the high-speed on-chip oscillator clock (f
IH
) as the main system
clock (f
MAIN
)
1 Selects the high-speed system clock (f
MX
) as the main system clock (f
MAIN
)
Notes: 1. Bits 7 and 5 are read-only.
2. Changing the value of the MCM0 bit is prohibited while the CSS bit is set to 1.
Caution: For details on the register setup procedures, refer to RL78/G13 User's Manual: Hardware.

Renesas RL78/G13 Specifications

General

Brand	Renesas
Model	RL78/G13
Category	Computer Hardware
Language	English