Renesas RZ/N1S

RZ/N1S Group CONNECT IT! ETHERNET RZ/N1S-DB
R01QS0021ED0060 Rev. 0.60 Page
13
of 24
Jan.31.2020
Table 9: Overview of IAR Projects for RZ/N1S
IAR Project
Description
CPU
Path to the workspace file in the Sol. Kit
YCONNECT-IT-RZN_V1.x\Software\...
x-ware*
Set of projects
running on the
Cortex A7
including ThreadX,
NetX Duo and
GUIx sample
applications
Cortex A7
\ThreadX\rzn1\iar\x-ware_platform.eww
GOAL
Projects**
Several example
projects showing
the different
functionalities for
the switch
management and
GOAL
Cortex M3
\GOAL\goal\projects\00410_goal\
Protocol
Stack
Projects***
Several Protocol
Stack slave
application
examples, which
are running I/O
communication
between a PLC
and RZ/N1S
Cortex M3
\GOAL\goal\projects\goal_ecat\
\GOAL\goal\projects\goal_eip_lib\
\GOAL\goal\projects\goal_epl_lib\
\GOAL\goal\projects\goal_mbs\
\GOAL\goal\projects\goal_pnio_lib\
* x-ware User Guide:
\YCONNECT-IT-RZN_V1.X\Software\ThreadX\rzn1\docs\X-Ware_Platform_RZ_N1_User_Guide.pdf
** GOAL application notes document:
\YCONNECT-IT-RZN_V1.X\Software\GOAL\doc\r11qs0008ed0131-rzn1-goal-quick-startguide-management.pdf
*** Protocol Stack quick start guides:
\YCONNECT-IT-RZN_V1.X\Software\GOAL\doc\r01an4239ej0090-rzn1-ethercat.pdf
\YCONNECT-IT-RZN_V1.X\Software\GOAL\doc\r11qs0007ed0131-rzn1-goal-quick-startguide-eip.pdf
\YCONNECT-IT-RZN_V1.X\Software\GOAL\doc\r11qs0010ed0131-rzn1-goal-quick-startguide-profinet.pdf
\YCONNECT-IT-RZN_V1.X\Software\GOAL\doc\r01an4412ej0090-rzn1-modbus.pdf
\YCONNECT-IT-RZN_V1.X\Software\GOAL\doc\r11qs0009ed0131-rzn1-goal-quick-startguide-powerlink.pdf
3. Write U-Boot to QSPI flash on the board
As you can see in Table 8, U-Boot is chosen as the secondary bootloader. It runs on the Cortex A7,
initializes some of the required interfaces and peripherals and it can be used to load software images for
both cores, by setting the corresponding parameters in the U-boot user console. Without U-Boot, you
cannot initiate the load of your application via IAR I-Jet Debugger to SRAM for executing on the target.
Figure 3-1 provides an overview of execution stages during programming U-Boot in Flash and later when
U-Boot is configured to read Cortex M3 and Cortex A7 Images from Flash and execute them.
After hardware reset, BootROM will start looking for the U-Boot package in QSPI. Therefore, you need to
write U-Boot in QSPI. This is done via USB DFU (Device Firmware Update). SW5 button pressed together
SW4 signals to BootROM, to switch the boot mode from QSPI to USB DFU. This is required only once, to
load U-Boot to SRAM. In the next step, you will write the U-Boot in flash. Please make sure to connect
CN3 on the board to a USB Host connector on your PC. This provides USB DFU.