Chapter 2 Command System RIGOL
DL3000 Programming Guide 2-11
:STATus:PRESet
Clears all the bits in the event register part of the questionable status register.
Remarks The event registers that have been cleared include query event enable register, channel
summary event enable register, and operation event enable register. Other registers will
not be affected by the command.
Example :STAT:PRES /*Clears all the bits in the event register part of the questionable status
:STATus:OPERation:CONDition?
:STATus:OPERation:CONDition?
Queries the operation condition register of the questionable status register.
Remarks The query returns a decimal value. It corresponds to the binary-weighted sum of all
the bits in the register. The definitions for the bits in the questionable status register
and the decimal value that corresponds to the binary-weighted value are shown in
Table 1-1.
It is read-only, and keeps the real-time (unlatched) operation state of the load.
The command is not exclusive to the channel. It is applicable to the mainframe.
Return
The query returns a decimal value. It corresponds to the binary-weighted sum of all the
bits in the register. For example, the query returns 1.
Example :STAT:OPER:COND? /*Queries the operation condition register of the questionable
status register. The query returns 1.*/
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