Rohm PMIC BD96801 - JTAG Interface

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© 2022 ROHM Co., Ltd.
65UG018E Rev.001
July 2022
User’s Guide
CN503
IO_L1P_T0_AD0P_15
Pin 1
Pin 11
IO_L6N_T0_VREF_15
IO_L1N_T0_AD0N_15 Pin 2 Pin 12 IO_L7P_T1_AD2P_15
IO_L2P_T0_AD8P_15 Pin 3 Pin 13 IO_L8P_T1_AD10P_15
IO_L3P_T0_DQS_AD1P_15
Pin 4
Pin 14
IO_L8N_T1_AD10N_15
IO_L3N_T0_DQS_AD1N_15 Pin 5 Pin 15 IO_L9P_T1_DQS_AD3P_15
IO_L4P_T0_15 Pin 6 Pin 16 IO_L9N_T1_DQS_AD3N_15
IO_L5P_T0_AD9P_15 Pin 7 Pin 17 IO_L10P_T1_AD11P_15
IO_L5N_T0_AD9N_15
Pin 8
Pin 18
IO_L10N_T1_AD11N_15
IO_L6P_T0_15 Pin 9 Pin 19 IO_L11P_T1_SRCC_15
GND Pin 10 Pin 20 V_1.8
Table 5: Pin-out connector CN503
3.9. JTAG interface
To access the Spartan-7 FPGA, the board offers a JTAG connector interface to read and write data to the FPGA.
Figure 7: JTAG connector
CN501
open Pin 1 Pin 2 V_1.8
GND
Pin 3
Pin 4
TMS
GND
Pin 5
Pin 6
TCK
GND Pin 7 Pin 8 TDO
GND Pin 9 Pin 10 TDI
GND
Pin 11
Pin 12
open
GND Pin 13 Pin 14 open
Figure 8: Pin-out JTAG connector