7/36
© 2022 ROHM Co., Ltd.
65UG018E Rev.001
July 2022
User’s Guide
The heart of the board is the Spartan-7 FPGA. It connects to a 128Mb flash memory device and a 4Gb DDR3L memory IC. It is clocked
by an external oscillator.
The system is powered by a primary buck controller BD9F500, a secondary PMIC BD96801 as well as a termination regulator
BD35395. The PMIC has preconfigured OTP settings which defines all required power settings, such as output voltages, protection
levels and voltage up- and down-sequencing. If needed, these settings can be adjusted by programming an onboard EEPROM via
I2C interface. If the EEPROM is not empty, the PMIC is initialized with its content during start-up.
The programmable flash memory transfers its code into the FPGA during start-up. A user can program its own FPGA code into the
flash memory device via the onboard JTAG port.
For maximum design flexibility, the EVK has 4 free programmable user switches as well as 36 free-of-use FPGA I/Os routed to two
connectors.
3.2. Board details
The main specifications for the evaluation board are summarized in Table 1 below.
V
IN
EVK Input voltage 10 V to 24 V
V_5.0 Output voltage BD9F500QUZ 5.0 V
I
OUT0
Max. output current BD9F500QUZ 5 A
f
SW0
Switching frequency BD9F500QUZ 1 MHz
V_1.8 Output voltage BD96801 buck1 1.8 V
V_1.35 Output voltage BD96801 buck2 1.35 V
V_1.0 Output voltage BD96801 buck3, buck4 (dual phase) 1.0 V
V_2.5a Output voltage BD96801 LDO5 2.5 V
V_2.5b Output voltage BD96801 LDO6 2.5 V
V_3.3 Output voltage BD96801 LDO7 3.3 V
I
OUT1
Max. output current buck1 2 A
I
OUT2
Max. output current buck2 2 A
I
OUT3,4
Max. output current buck3,4 (dual phase) 8 A
I
OUT5
, I
OUT6
, I
OUT7
Max. output current LDO5, LDO6, LDO7 300 mA
f
SW
Switching frequency BD96801 2.25 MHz
T
OPR
Operating temperature -40°C to 125°C
Table 1: Specification of evaluation board