Roland SDE-3000 Service Notes

FEB. 5,1984
SDE-1000/3000
D/A CONVERTER
When the time determined by DELAY TIME has passed, some parts of A/D
system serve as D/A converter. RAM stored 12-bit data is transferred in time
sequence (3 bits parallel x 4 times) from each RAM OUT pin to IC12 where
they are so arranged that they are fed simultaneously via D11-D10, ICs 3,4,
RM-1, Q9 and Q10 to S/H IC5C and IC5D.
EXPANDER
One half IC15 NE570 exponentially amplifies delayed audio to restore it to
the original dynamic range.
LPF-2
The configuration analogues to LPF-1, providing 19kHz bandwidth when
Q48 is ON, or 9.5kHz when Q49 is selected by TIME X2 switch. Being an
interporating filter, it smoothes staircase-like out of the waveform. As just for
LPF-1, mute signals are applied from Control Logic IC14.
DE-EMPHASIS
IC29 and associated components reduce higher frequency components in the
delay line to compensate for preemphasis, restoring the overall frequency res
ponse to flat.
PHASE SELECTOR
Q45, when conducted, change IC28 into an inverter, reversing the delay out
put phase with respect to the direct signal.
DELAY PHASE "OFF"
INPUT
MIXED
OUT jack
INPUT
MIXED
OUT jack
DELAY OUT (VR4)
at CENTER
MAIN CONTROLLER
IC12 63H-101 a specially designed gate array for controlling digital delay
system. It clocks most of delay related sequences such as A/D, D/A, S/H,
RAM accessing, etc. in time with clocks generated at the internal timing gene
rator which in turn is clocked on MSCK delivered from CLOCK Generator
IC23. With TIME X2 button activated IC12 has an H on RNG 1 pin and slows
down all timing sequences by one-half except REFRESH cycle. The clock fre
quency can be varied by the external voltages to be applied on FC pin or PA
pin.
As the name implies, IC12 Main Controller is the heart of the Delay Line. All
the delay circuits will not work correctly should the Main Controller fail to
receive adequate clocks from IC23.
IC12 PIN DESCRIPTION
SAH & RNG 1
SAH determines the rate of sampling being performed at IC5 which gates on a
high SAH. When TIME X2 is engaged, RNG 1 turns from L to H, lengthening
SAH intervals from 22.9/is to 45.8/us
DIN
D IN accepts a series of H or L from the comparator IC2, resetting register(s)
in SAR on H to omit it from the subsequent comparisons.
DOUT
These Hs and Ls on D IN are also transferred to RAMs (IC9-IC11) and stored
as a set of 12-bit data which represint the amplitude of a portion of input
signal (sampled audio) being fed to I(2 pin 2.
D0-D11
During A/D conversion cycle these pins represent comparison data from
internal SAR. During D/A cycle, sinultaneously output 12-bit RAM stored
data which have been read from eaci RAM in time sequence (3-bits x 4) and
temporarily buffered in internal threi registers.
A0-A7
These pins feed RAMs with addresses: Refresh, Row and Column. Since the
number of RAM cells involved in data storage is varied with DELAY TIME
setting, the numbers of Row and Column addresses are also changed accord
ingly while Refresh addresses are issued for all the RAM cells.
RS(RAS) 16
Falling edges of RAS (Row Address Strobe) enable each RAM to latch Row
address (W/R cycle) or Refresh address into its designated cells.
CAS1-CAS3
RAMs IC9—IC11 latch Column addresses on negative edges of cocurrent
Column Address Strobes (CAS1CAS3) which also serve as Chip select, and
read memory cell respectively. The data read are routed to the RAM D
OUT (pin 14) while related CAS is low.
DATA & SHI FT (SIFT)
As mentioned in general descriptio,
RAM cells used for sound memory <e
varied with time delay. IC12contds
RAMs accessing sequence in accod-
ance with DELAY TIME DA>
received at SHIFT rate. The DATAIs
a serial stream of 16 bits and'vti
change between:
, 16 bits—,
MSB LSB
0000 000 at 0ms setting am
0011 111 at maximum settg
11 (SDE-3000)
The DATA/SHIFT are transmit^
only after DELAY TIME or PRESf
button is released.
The DATA is accompanied by sevel
mute signals to cancel unwantl
signals.
MUTE A: active low when DEL/
TIME button is mai-
plated.
MUTE B: active low while PREST
is pressed.
To shorten the Mute periods, TIC
X2, MOD., and X1.5 are disabled.
CPU .
(IC21)
IC17
P20(DATA)
P21 (SHIFT)
P22(X1.5INH)
P23 (MUTE A)
^ P23 (MUTE B)
Q2(TIMEX2)
- Q4 (MOD)
Interruption(s) for Switch scan and LED/numerical displays.
MINIM
L
TIME/MEMORY
DELAY TIME DATA

Roland SDE-3000 Specifications

General

Type	Digital Delay
Output Impedance	1 kOhm
Inputs	1/4" phone jack
Outputs	1/4" phone jack
Total Harmonic Distortion	0.05%
Power Supply	AC 117 V