JUN.
15,
1981
TR-808
CIRCUIT
DESCRIPTION
TR-808
TEMPO
CLOCK
EMPo L
T.
FF
INTEEEUPT
CLOCK
<.TBP LEDa
STEP
5W/^
JI
II
PUMCT'OU
Jl
b
p^
PB
PI
I
PH
CPU
PC
CPU
cLOci;
TRI6<5-Ee
MDWO
MC/LTI
PECODEZ
1
f;
TlCCEA/r
([
N
j^
MEMORY
APDJtESS
-1^
b
PIN
CONNECroe
^/ite
Thick
line indicates
CPU
controlled
circuits,
thin line
Voicing.
f
&
HflSTEe
OUT
MULTI OUT
^
M
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FIGURE
1 BLOCK
DIAGRAM
MPD650C-085
FUNCTIONAL DESCRIPTION
No.
PH
26
(PortH)
1 27
Scanning signal outputs
to switches
2 28
Switching signal
outputs to STATUS BUFFER
&
GATE
3
29
PA
33
(Port
A) 1 34
Switch scanning signal inputs
2
35
STATUS
(TEMPO.
CLOCK. START/STOP. FILL IN) inputs
3 36
PB
37
(Port
B) 1
?
38
39
Inputs from
STEP Switches (RHYTHM SELECT Swtiches)
3 40
PG
22
(PortG)
1
2
3
23
24
25
Drive signals
to
STEP
LEDs
PE
12 1st/2nd CP
(Port E)
1 13 A/B RS
2 14
Memory
bank
HT
3 15
select
MEMORY ADDRESSES
MT
CH
INSTRUMENT
DATA
PD
n
R
(Port
D) 1
2
9
10
Dk,,+i,„
These pins use CE from
nnluZ
ADDRESS
Decoder to
numoers
select cells in
RAM to
OH
CY
These
data
need
COMMON TRIG to
trigger
Sound Generators
3 11
be accessed
CB
LT
being designated
PF
16
(Port F)
1 17
Step
SD
2 18
numbers
BD
3 19
AC
PC
2
(Port
C) 1
2
3
3
4
5
Data Inputs/Outputs
PI
30 Memory WE
(Port
1)
1 31 Memory CE (associated with PE-2,
3 at ADDRESS
DECODER)
2 32 Trigger Pulse (INSTRUMENT) output
General
As can be seen from the
block
diagram, most processes of
TR-808 up
to generation
of pulses
triggering sound
generators
are
controlled
by
the
computer.
CPU
pin
functions
are
as
shown
at
the
lower left table.
Once
power is turned
on for
TR-808, pulses are
generated from PI-2
of
CPU regardless of
TR-808
function mode
(Start/Stop)
and of
presence
or absence of
rhythm
patterns. The
time length between
the
pulses
is equal to that of
the shortest rhythm
patterns.
The pulse
is transfered
to TRIGGER
MONO, then
ACCENT from which it is
applied in
parallel
to
all the
gates prestaged to
Sound Generators;
accordingly,
called
COMMON
TRIGGER.
On the other hand, instru-
ment
data
designating
sound
to be outputted are independently
supplied
to the
gates from
corresponding exclusive
ports (PD,
PE
and PF).
Since
Instrument
data are time
sharing the
data buss
with
memory
addresses,
the
data
are
aligned with Common
Trigs in timing.
When
these
two
signals are
applied, the gate
ANDs
the
two signals
and
outputs
a
signal triggering
the sound
generator. Since the
peak
value
of
this trig signal
is in proportion
to that of the
Common
Trig pulses,
when an accent
data is outputted, the
data
can
be used
to change the
amplitude of the
Common Trig signal.
Panel
control settings
are read
by interruption of
CPU each time
an interrupt
signal is fed
to
the
INT terminal. First, the Buffer
&
gate turns on
by a
signal
from
PH,
and the
status is
read
through
PA.
Then, some
statuses of
function switches
are read through
PA by
a signal
from one
port of
PH.
At
the
same time, some
statuses of
a
group of
step switches
are read through PB,
and the
step LED drive
signa
l is
outputted from PG
as required.
Statuses are read each time
an
INT signal
is fed.
However,
statuses
of
the step and function
switches
are read
every four times
of INT signals.
Four
CMOS RAMs (IK
x 4-bit) are used for
data storage. Chips are
selected when
the
upper two bits of PE
data decoded
by IC5 are
enabled
by pulses from
PI-1.
Addresses of chip
memory cells are
designated
by bits of PD, PE
and
PF.
Data storage to addresses
are
possible when
an
L output from PI-0
is applied
to
WE
.
Detail
SW
Scanning,
Status Reading
Reading
of statuses of the
controls on the
panel (step
switches,
function
switches, tempo,
etc.) starts when
an interrupt signal is
applied
to
INT terminal every 1.9ms.
When the signal
is applied
to
INT
terminal,
CPU starts interruption. The
interruption period
is
approx.
600)Us. During the first
150ms,
PH0-PH3
become H, and
the
colle"ctor of
AND gate
Q18 becomes
L.
STATUS signals are
ANDed
with this
L
by IC3 and read through
PA. After
150axs,
only
PH-0
becomes
L.
This signal is
converted
to H by
Q23,
and reaches
PB
and PA
through the
closed
contacts
of the
Step switches (No.
1
—
No.
4),
SWla (Mode)
and SW2 (Clear). When
one of the four
Step
switches is
closed, the
corresponding
STEP LED lighting
signal
is
immediately
fed from
PG. Since the
PG output is latched
until the
next
INT
signal is
applied,
the
lighting
period is approx. 1.8ms.
This
period
b is approx.
450jus. The remaining period
c is for processing
of
main
program. When the
next INT signal
is applied,
PHO—
PH3
become
H again, the
statuses of the TEMPO
CLOCK,
START/STOP,
TAP,
etc. are
read again. Then,
only PHI becomes
L
and the statuses
of
switches
connected
to
the
collector
of 024 are read.
At
the next
INT signal,
STATUS
and PH2
become
L.
Next, PH3
becomes
L.
This change
is repeated.
In
this
way statuses are checked
each time an
INT signal is
applied every
1.9ms so that the CPU
can respond to the
status change
promptly. The
statuses of other switches
are read every
four
times of
INT signals. This
corresponds
to one reading every
7.6ms.
INTEREUPT
CLOCK
ICl
pin 6
—
1,9ms
—
PHO
PHo
7. 6ms
-
active
low
STEP
1-4
MODE
CLEAR
STEP
5-8
PRESCALE
BASIC
VARI,
STEP
9-12
INSTR.
SELECT
INSTRUMENT
SELECT
STEP
13-16
AUTO
FILL
IN
I/F
VARIATION
TEMPO
CLOCK
START
/ST
OP
TAP
FIGURE
2
INTERRUPT
CYCLE
TIMING
DIAGRAM
INTERRUPT
CLOCK
PH
a
'
b
^
450;is
STATUS
GATE
,
All
time lengths
are approximate.
15Q)as
Ql8
rrr
START/STOP
RESET
&
START
TEMPO
CLOCK
IC3
FIGURE
3
SCANNING]
SIGNAL
FLOW
PG
outputs
1.8ms
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