TR-808
JUN.15,1981
PCo
PC,
CPU
I
R85-R88
—
^AV
^FD4^C
^vw
^Wv-
-AW-
m-
Ttr
rrr
FIGURE 4
RAM
MEMORY MAP
COW_
BELL
CYMBAL
OPEN
HI^HAT_
CLOSED
hi" HAT
Ic
8
MID
TOM
TOM
HIGH
TOM
TOM
RIM
^HOiy
~_'
HAND
CLAP
"
TcIO
ACCENT
BASS_DRl]M___
~_SNARE
DRUM
LOW TOM~TOM
lc7
RHYTHM TRACK
RHYTHM PRESCALE
RHYTHM
STEP
Icl
CPU
PI-]^
Memory
CE
lOus
lOus lOus
VALib ADbRESS
1
READ CYCLE
IC7-IC10
pins
11-14
PC
0-3
Data
read
STOiRED
DATA]
-<
—
^
WRIT^ CYCLE
4
PC
0-3
Data
write
CPU PI-0_
Memory
WE
DATA
in
RAM
WRITE DATA
RAM,
Address Decoder
Four
static CMOS RAMs (/iPD444C,
1 K x
4-bit) are used
for memory.
The
memory map is shown in Fig.
4.
The upper
two bits
PE2
and PES of
CPU
designate a RAM, IC5
decodes
these bits, and the
memory select
is enabled
by a
signal from
PI-1
(CE).See Fig.
5.
Cell addresses
are designtated
by
bits from
PD, PE
and
PF.
After lO^us
of CE,
the
data
shown in Fig.
5-2
is read (5-3) or
a
new
data
from
PC is written
(Fig. 5-5).
As
can
be seen from Fig.
5-2
and
-4, during
writing, PC output data
and RAM
data at
the
I/O ports of RAM may conflict
with one
another.
To prevent this, the
buffer resistors {R85—
R88)
are
con-
nected.
The
LED driver
transistors (Q2-Q5) for
BASIC
VARIATION,
1ST
and 2ND are directly connected
to the bus of
PD
and
PE.
However,
since various
data appear on the
bus by
time sharing processing,
the
LEDs may sometimes light even when unnecessary signals are
applied,
resulting in
possible
lighting
timing disparity in
a
mode.
RAMs' low power consumption during high
CE
allows memories to
be maintained for longer period
with back-up battery.
PI-2
CPU
pin_$2
IC6
pin
10
PD
PE
PF
STBLE
INSTRUMENT
DATA
FIGURE
6
TRIG-INSTRUMENT
Trigger
Gate
Pulses
corresponding
to
the
shortest rhythm
step
usable
by TR-808
are fed
from PI-2
of
CPU at
a
time
interval
determined
by the setting
of
TEMPO
CONTROL (Fig.
6-1).
On the other
hand,
instrument
data
to be reproduced
are
applied
from PD, PE
and PF
to
the
gate
of
each
sound generator
in
synchronization
with
step
pulses (Fig.
6-3).
Since
the
step pulse
width of
10)Us
is
too narrow
to trigger
a sound
generator,
it is
widened
to approx.
1ms which
is nearly
equal
to
the
width
of
instrument
data signal.
This widening
is accomplished
by
the
monostable
IC6.
It
is
triggered
by a rising edge of
Q27-inverted
pulse.
(Fig.
6-2). The
L period is
determined
by
the
sum of the
time
constants of
R
1
00 x
C23 and
R
1
02 x
C27.
The
output from
pin
10
of
IC6 passes through the
ACCENT circuit
composed of
031
-034, becomes
a
COMMON TRIG signal,
and
simultaneously
applied
to the gates of
all sound
generators
in parallel.
When
instrument
data
is
present
at a gate, this trigger
signal is
ANDed
with the
data and
activates the
corresponding
sound
generator
(See
Fig.
7).
Since the
AND
output from
the
gate is in
proportion
to
the
amplitude
of the
common
trig
signal, the
output of the
sound generator
has the
amplitude
in
proportion
to the
common trig
signal.
Accordingly,
when
ACCENT
data are
present, they
are
added to the common
trig
signal.
Since the
output
of
pin
10 of IC6 is
a negative logic signal,
when
there
are
no
step
pulses, the
output signal
becomes
H, 031
turns on
and
places
a ground
at base of
032. When
pin
10
of
IC6
becomes
L,
031 becomes
off, and
when
ACCENT
data from
PF-3
is
L
(no
accent),
034 turns
on
to
shunt
VR3.
As a
result, the
base of
032 becomes
approx.
+5V and
trig amplitude
is
approx.
4V.
When
ACCENT
data
is
H,
a voltage
between
5V and
15V according
to VR3
setting is
applied
to the
base of
032,
and
is converted
into trig
pulses
of
approx.
4-14V. This
explains
that
ACCENT level
can be
changed
by
VR3.
In the
case
of
CB, CY,
OH and
CH, trig variation
range
is narrowed
to 7V-14V
by
1/2
IC2 (pins 1-3)
on the
voicing
board to increase
S/N ratio.
DATA TIMING
COMMON
TRIG
prestored
FIGURE
5 READ/WRITE CYCLE TIMING
new or
refreshed
Ims
It"
a
ACCENT
ACCENT
FIGURE 7
VOICE GENERATOR
TRIGGER
PULSE
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