Samsung Electronics
Service Manual
System Overview
3-14
3.2.3.3 Asic(SPGPv3)
CPU Core : ARM1020E
- 32KB instruction cache and 32KB data cache
Operating Frequency
- CPU Core : over 300MHz
- System Bus : 100MHz
SDRAMC
- 32Bits Only, 100MHz
- 5 Banks (Up to 128MB per Bank)
ROMC
- 4 Banks (Up to 16MB per Bank)
IOC
- 6 Banks (Up to 16MB per Bank
DMAC
- 4 Channels
HPVC
- Dual/Single Beam
- LVDS Pad(VDO, HSYNC)
UART
- 5 Channels (1 Channels Supports DMA Operation)
PCI Controller
- 32Bits, 33/66MHz
- PCI Local Bus Specification rev2.2 Complaint
- Host / Agent Mode (Support 4 Devices in Host Mode)
NAND Flash Controller
- 8/16Bits, H/W EEC Generation
- Auto Boot Mode (Using Internal SRAM, 4KB)
MAC
- 10M/100Mbps
- Full IEEE 802.3 Compatibility
Engine Controller
- LSU Interface Unit
- Step Motor : 2 Channels
- PWM : 8 Channels
- ADC : 6 Channels
I2C Controller
- I2C(S-BUS) Slave Device Support(I2C Version 2.1)
RTC
- RTC Core Voltage : 3V
PLL
- 3 PLL : MAIN, PCI, PVC
3.2.3.4 Memory
Flash Memory : It stores System Program and downloads the System Program through PC Interface, and in case of
model for export it compresses the PCL font, then stores it.
- Capacity : 8M Byte (Nor Flash)
- Random Access Time : 10 us (Max)
- Serial Page Access Time : 50ns (Min)
DRAM : It is used as Swath Buffer, System Working Memory Area, etc. when printing.
It stores Font List, compressed into Flash memory, on DRAM and uses it as PCL font in case of model for export.
- Capacity : 32M Byte(STD/MAX)
- Type : SDRAM 100MHz/133MHz, 16bit
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