Samsung S3C2416 - Bank Onenand Type Selection Register; SMC Status Register

S3C2416X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER
5-19
4.7 BANK ONENAND TYPE SELECTION REGISTER
Register Address R/W Description Reset Value
SMBONETYPER 0x4F000100 R/W SMC Bank OneNAND type selection
register
0x0
Bit Description Initial State
[31:6] Read undefined. 0x0
BANK5TYPE [5] 0 = DEMUXED OneNAND
1 = MUXED OneNAND
0x0
BANK4TYPE [4] 0 = DEMUXED OneNAND
1 = MUXED OneNAND
0x0
BANK3TYPE [3] 0 = DEMUXED OneNAND
1 = MUXED OneNAND
0x0
BANK2TYPE [2] 0 = DEMUXED OneNAND
1 = MUXED OneNAND
0x0
BANK1TYPE [1] 0 = DEMUXED OneNAND
1 = MUXED OneNAND
0x0
[0] Reserved 0x0
NOTE: Type of bank0 OneNAND is determined by OM[4:2] signals (See table 1-4).
4.8 SMC STATUS REGISTER
Register Address R/W Description Reset Value
SMCSR 0x4F000200 R SMC status register 0x0
Bit Description Initial State
[31:1] Read undefined. 0x0
WaitStatus [0] External wait status, read:
0 = nWAIT deasserted.
1 = nWAIT asserted.
After an externally waited transfer that was terminated early,
this bit value can detect when
nWAIT is deasserted. At all other times, this bit reads zero.
0x0