S3C2416X RISC MICROPROCESSOR UART
14-7
2.1.7 UART Error Status FIFO
UART has the error status FIFO besides the Rx FIFO register. The error status FIFO indicates which data, among
FIFO registers, is received with an error. The error interrupt will be issued only when the data, which has an error,
is ready to read out. To clear the error status FIFO, the URXHn with an error and UERSTATn must be read out.
For example,
It is assumed that the UART Rx FIFO receives A, B, C, D and E characters sequentially and the frame error
occurs while receiving 'B', and the parity error occurs while receiving 'D'.
The actual UART receive error will not generate any error interrupt because the character which is received with
an error would have not been read. The error interrupt will occur once the character is read.
Figure 14-3 shows the UART receiving the five characters including the two errors.
Time Sequence Flow Error Interrupt Note
#0 When no character is read out
−
#1 A, B, C, D, and E is received
−
#2 After A is read out The frame error (in B) interrupt occurs. The 'B' has to be read out.
#3 After B is read out
−
#4 After C is read out The parity error (in D) interrupt occurs. The 'D' has to be read out.
#5 After D is read out
−
#6 After E is read out
−
-
-
-
-
-
-
-
-
-
-
-
'E'
'D'
'C'
'B'
'A'
Rx FIFO
URXHn UERSTATn
break error parity error frame error
Error Status Generator Unit
Error Status FIFO
Figure 14-3. Example showing UART Receiving 5 Characters with 2 Errors
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