Samsung S3C2416 - Clock, EPLL Speed Guide

S3C2416X RISC MICROPROCESSOR UART
14-11
2.1.11 Baud-Rate Error Tolerance
UART Frame error should be less than 1.87%(3/160).
UART Frame error = { |Real Frame Length − Ideal Frame Length| / Ideal Frame Length } x 100%
= { |Ideal baudrate − Real baudrate| / Real baudrate } x 100%
Real Frame Length = 1 Frame / Real UART baudrate = 1 Frame x (DIV_VAL+1) x 16 / SRCCLK
Where Real UART baudrate = { SRCCLK / (DIV_VAL+1) } / 16
Ideal Frame Length = 1 Frame / Ideal UART baudrate
NOTE
1Frame = start bit + data bit + parity bit + stop bit.
2.1.12 UART Clock and PCLK Relation
The frequency of UARTCLK(Clock of 16 times baud-rate) must be no more than 5.5/3 times faster than the
frequency of PCLK :
F
UARTCLK
<= 5.5/3 X F
PCLK
F
UARTCLK
= baudrate x 16
This allows sufficient time to write the received data to the receive FIFO
Parameter Symbol Min Typ Max Unit
PCLK speed for UART operating (Baudrate is 1Mbps)
F
PCLK
8.72
− −
MHz
PCLK speed for UART operating (Baudrate is 2Mbps)
F
PCLK
17.45
− −
MHz
PCLK speed for UART operating (Baudrate is 3Mbps)
F
PCLK
26.18
− −
MHz
2.1.13 UART Clock speed/UART Clock selection guide for 3Mbps
For using 3Mbps, EPLL should be either 48MHz or 96MHz. Or EXTUARTCLK should be 48MHz.
Table 14-3. Clock, EPLL Speed Guide
Parameter Min Typ Max Unit
UART source clock(divided EPLL clock)
− −
50 MHz
EPLL clock for divided EPLL clock(by UARTDIV of CLKDIV1, refer
Figure 2-9)
− −
100 MHz
EPLL clock(UART source clock is divided EPLL) (3Mbps)
−
48, 96
−
MHz
EXTUARTCLK (UART source clock is EXTUARTCLK)
− 48
MHz
Baudrate (UART source clock is EXTUARTCLK, divided EPLL clock)
−
3,000,000 bps
When SRCCLK is PCLK, Integer part of DIV_VAL should be equal or larger than 1(divide SRCCLK by 2). Hence
maximum baudrate is limited. (2.0625Mbps at typical PCLK 66MHz)