DMA CONTROLLER S3C2416X RISC MICROPROCESSOR
8-4
3.1 EXTERNAL DMA DREQ/DACK PROTOCOL
There are four types of external DMA request/acknowledge protocols. Each type defines how the signals like
DMA request and acknowledge are related to these protocols.
3.1.1 Basic DMA Timing
The DMA service means paired Reads and Writes cycles during DMA operation, which is one DMA operation.
The Figure 8-1 shows the basic Timing in the DMA operation of the S3C2416.
• The setup time and the delay time of XnXDREQ and XnXDACK are same in all the modes.
• If the completion of XnXDREQ meets its setup time, it is synchronized twice and then XnXDACK is asserted.
• After assertion of XnXDACK, DMA requests the bus and if it gets the bus it performs its operations. XnXDACK
is deasserted when DMA operation finishes.
XSCLK
9.3ns Setup
9.3ns Setup
6.8ns Delay
6.6ns Delay
Read Write
Min. 2MCLK
XnXDREQ
XnXDACK
Min. 3MCLK
Figure 8-1. Basic DMA Timing Diagram
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