Sanyo DC-X8CT - IC Block Diagram & Description

- 55 -
Clock generating
circuit
Watchdog
timer
R A M
R O N
A-D
converter
(10)
PWM
(8)
P4(5) P3(5) P2(8) P1(8) P0(8)
SI/O(8)
Prescaler 12(8)
Prescaler X(8)
Prescaler Y(8)
Timer 1(8)
Timer 2(8)
Timer X(8)
Timer Y(8)
C P U
A
X
Y
S
PC
L
PS
PC
H
INT 0 -
INT
3
Reset
Sub-
clock
input
X
CIN
Sub-
clock
output
Xco
UT
CNTR 0
CNTR 1
XCOUT
XCIN
18 15
1
21
2019
2
34
5
6
7
8
9
10
11
12 13
14
16
17
38 39
40
41
42
22 23
24
25
27
29
30
31
32
33 34
35 36
37
2826
X
IN
X OUT V SS V CC
CNV SS
RESET
P4
4
/INT
3
/PWM
P4
3
/INT
2
P4
2
/INT
1
P4
1
/INT
0
P4
0
/CNTR
1
V
REF
AV
SS
P2
7
/CNTR
0
/S
RDY
P2
6
/S
CLK
P2
5
/T
X
D
P2
4
/R
X
D
P2
3
P2
2
P2
1
/X
CIN
P2
0
/X
COUT
P3
0
/AN
0
P3
1
/AN
1
P3
2
/AN
2
P3
3
/AN
3
P3
4
/AN
4
P0
7
P0
6
P0
5
P0
4
P0
3
P0
2
P0
1
P0
0
P1
0
P1
1
P1
2
P1
3
/(LED
0
)
P1
4
/(LED
1
)
P1
5
/(LED
2
)
P1
6
/(LED
3
)
P1
7
/(LED
4
)
i
npu
t
ou
t
pu
t
Reset
input
IC331 M38503M4 ( Syngle-Chip 8-Bit CMOS Microcomputer )
IC BLOCK DIAGRAM & DESCRIPTION
No. Pin Name FUNCTIONS
Function ex except a port function
1 VCC Power Source Apply voltage of 2.7V-5.5V to VCC, and 0V to VSS.
2 VRFF
3 AVSS
4 P44/INT3/PWN I/O port P4 78-bit CMOS I/O port with the same function as port P0. 7Interrupt input pins
7PWM output pin
5 P43/INT2 I/O port P4 7CMOS compatible input level. 7Interrupt input pins
6 P42/INT1 I/O port P4 7CMOS 3-state output structure.
7 P41/INT0 I/O port P4
8 P40/CNTR1 I/O port P4 7Timer Y function pin
9 P27/CNTR0/ I/O port P2 78-bit CMOS I/O port. 7Serial I/O function pin/
SRDY 7I/O direction register allows each pin to be individually Timer X function pin
10 P26/SCLK I/O port P2 programmed as either input or output. 7Serial I/O function pin
11 P25/TXD I/O port P2
12 P24/RXD I/O port P2 7CMOS compatible input level.
13 P23 I/O port P2 7P20,P21,P24 to P27: CMOS3-state output structure.
14 P22 I/O port P2
7P22,P23,N-channel open-drain structure.
15 CNVSS CNVSS Input 7This pin controls the operation mode of the chip.
7Normally connected to VSS.
16 P21/XCIN I/O port P2 78-bit CMOS I/O port.
7Sub-clock generating circuit I/O
17 P20/XOUT I/O port P2 7I/O direction register allows each pin to be individually pins(connect a resonator)
programmed as either input or output.
7CMOS compatible input level.
7P20,P21,P24 to P27: CMOS3-state output structure.
7P22,P23,N-channel open-drain structure.
18 RESET Reset Input 7Reset input pin for active "L".
19 XIN Clock Input
7Input and output pins for the clock generating circuit.
7Connect a ceramic resonator or quartz-crystal oscillator
20 XOUT Clock Output between the XIN and XOUT pins to set the oscillation frequency.
7When an external clock is used, connect the clock source to
the Xin pin and leave the Xout pin open.
21 VSS Power Source 7Apply voltage of 2.7V-5.5V to VCC, and 0V to VSS.
22 P17 78-bit CMOS I/O port.
23 P16
24 P15 7I/O direction register allows each pin to be individually programmed
25 P14 I/O port P1 as either input or output.
26 P13
27 P12 7CMOS compatible input level.
28 P11
29 P10 7CMOS 3-state output structure.
30 P07
31 P06 7P13 to P17(5 bits) are enabled to output large current for LED drive.
32 P05
33 P04 I/O port P0
34 P03
35 P02
36 P01
37 P00
38 P34/AN4 78-bit CMOS I/O port with the same function as port P0. 7A-D converter input pin
39 P33/AN3
40 P32/AN2 I/O port P3 7CMOS compatible input level.
41 P31/AN1 7CMOS 3-state output structure.
42 P30/AN0