Sanyo DP26670 - Ddr2

A B C D E F G H
A B C D E F G H
2
1
3
4
5
6
7
8
2
1
3
4
5
6
7
8
IC2801 R8J66975BG
SCALER IC
V2
P2
N4
T2
R4
P4
R2
R3
V1
R1
T4
W2
V4
W3
W1
U4
W7
W5
AB7
AA4
AA6
AB4
AA8
AA5
AB6
AB5
IC2802 H5PS5162FFR-S5C
DDR2_SDRAM IC
R1
G2
G8
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
M3
M7
N2
N8
P3
P7
R2
M8
P2
K7
L7
K9
L1
L3
L2
K3
K2
M9
J9
E1
A1
B8
D2
D8
E7
F2
F8
H2
H8
J7
A3
E3
J3
N1
P9
A7
B2
G9
G7
G3
C7
C9
E9
G1
C3
C1
A9
J1
AA9
Y9
Y5
Y1
V3
T5
N1
N5
T1
V7
R5
AB8
AA7
L8
M2
P8
N3
N7
J8
A8
B7
E8
F7
F3
B3
K8 AA1
Y2
P1
N2
U1
U2
N3
U3
AB3
Y4
W8
AA2
W9
Y6
AB2
AA3
W6
Y8
J2
R8
R7
R3
E2
A2
WAS RECEIVED IN GOOD CONDITION AND PICTURE IS NORMAL.
WITH THE DIGITAL TESTER WHEN THE COLOR BROADCAST
NOTE:THE DC VOLTAGE AT EACH PART WAS MEASURED
C2837
0.110V 1005B
C2979 0.110V 1005B C2964 0.110V 1005B C2963 0.110V 1005B
C2846 0.110V 1005B
C2811 1010V 2125B
C2813 0.110V 1005B C2816 0.110V 1005B C2818 0.110V 1005B C2820 0.110V 1005B C2822 0.110V 1005B
C2824 0.110V 1005B C2827 0.110V 1005B C2830 0.110V 1005B C2832 0.110V 1005B
C2812 0.110V 1005B C2814 0.110V 1005B C2817 0.110V 1005B C2819 0.110V 1005B
C2821 0.110V 1005B C2823 0.110V 1005B C2825 0.110V 1005B C2826 0.110V 1005B C2828 0.110V 1005B
C2831 0.110V 1005B
C2815
0.1
10V 1005
B
C2829
0.110V 1005B
C2833 0.110V 1005B C2834 0.110V 1005B C2835 0.110V 1005B C2836 0.110V 1005B C2838 0.110V 1005B C2839 0.110V 1005B C2840 0.110V 1005B
C2841_1
330
2.5V
CX
R2832
33 1/16W 1005
R2841
33 1/16W 1005
R2846
100
1/16W 1005+-1%
R2842
4.7
1/16W 1005
R2844
62 1/16W +-1%
R2809
200 1/16W
1005
+-1%
R2831
120 1/16W 1005
R2843
4.7
1/16W 1005
R2845
100 1/16W
1005+-1%
R2829
100 1/16W 1005+-1%
R2830
100
1/16W 1005+-1%
OF PRINTING AND SUBJECT TO CHANGE WITHOUT NOTICE
NOTE:THIS SCHEMATIC DIAGRAM IS THE LATEST AT THE TIME
NR2802
4D02WGJ0330TCE
NR2801
4D02WGJ0330TCE
NR2803
4D02WGJ0330TCE
NR2815
4D02WGJ0330TCE
NR2814
4D02WGJ0330TCE
SDDQ0
SDDQ1
SDDQ2
SDDQ3
SDDQ4
SDDQ5
SDDQ6
SDDQ7
SDDQ8
SDDQ9
SDDQ10
SDDQ11
SDDQ12
SDDQ13
SDDQ14
SDDQ15
DADQM0
DADQM1
DADQS0
DADQS0_N
DADQS1
DADQS1_N
DACLK SDCLK
DACLK_N SDCLK_N
SDBA2
SDBA1
SDBA0
SDODT
DRAM_A0
SDCKE
DRAM_A1
SDCS
DRAM_A2
DRAM_A3 SDRAS
DRAM_A4
SDCAS
DRAM_A5
SDWE
DRAM_A6
DRAM_BA1 SDBA1
DRAM_WE SDWE
DRAM_A7
DRAM_A2 SDA2
DRAM_A8
DRAM_CS SDCS
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_BA0 SDBA0
DRAM_BA2 SDBA2
DRAM_A12
DRAM_CKE SDCKE
SDA0
DRAM_A1 SDA1
SDA1
DRAM_RAS
SDA2
DRAM_CAS
SDA3
DRAM_ODT
DRAM_A9 SDA9
DRAM_CS SDA4
DRAM_A3 SDA3
DRAM_A7 SDA7
DRAM_BA2 SDA5
DRAM_A12 SDA12
DRAM_BA1
SDA6
DRAM_BA0
SDA7
DRAM_WE
DRAM_A8 SDA8
SDA8
DRAM_CKE
DRAM_A11 SDA11
DRAM_A5 SDA5
SDA9
DRAM_A10 SDA10
SDA10
SDA11
DRAM_CAS SDCAS
SDA12
DRAM_A0 SDA0
DRAM_A4 SDA4
DRAM_A6 SDA6
DRAM_RAS SDRAS
DRAM_ODT SDODT
D1.8V
GND
G-12G-11
DDR2 SCHEMATIC DIAGRAM
(DIGITAL PCB)
CEJ554
PCBDH0
FROM/TO REGULATOR
SDDQ1
SDDQ2
SDDQ3
SDDQ4
SDDQ5
SDDQ6
SDDQ7
SDDQ8
SDDQ9
SDDQ10
SDDQ11
SDDQ12
SDDQ13
SDDQ14
SDDQ15
SDDQ0
SDA1
SDA2
SDA3
SDA4
SDA5
SDA6
SDA7
SDA8
SDA10
SDA11
DDR DATA Interface
DDR Control
DDR Address
DQ0
DQ1
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
A0
A1
A2
A3
A4
A5
A6
A8
A9
A10
A11
A12
A7
RAS
CAS
ODT
CS
NC
BA0
BA1
WE
CKE
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VREF
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VCCQ18
VCCQ18
VCCQ18
VCCQ18
VCCQ18
VCCQ18
VCCQ18
VCCQ18
SDVREF1
SDVREF0
DD_CL
DDR POWER
SDA12
SDA9
LDM
UDM
LDQS
LDQS
UDQS
UDQS
CK
CK
SDDM0
SDDM1
SDDQS0
SDDQS0_N
SDDQS1
SDDQS1_N
SDDCLK
SDDCLK_N
SDA0
SDBA1
SDBA0
SDODT
SDCKE
SDCS
SDRAS
SDCAS
SDWE
SDBA2
NC
NC
NC
NC
NC NC5
NC4
NC3
NC2
NC1
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
0.9
0.9
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
0.9
1.8
0.9
1.8