Sharp CE-150 - Page 253

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All and more about Sharp PC -1 500 at http:// www .PC-1500.info
@ BRO
Bu s r <:q u cs t :; i gn al.
@ BAK
flu s req ue st ackowlcdgc signal. Wh en BRQ goes hig h. the CPU issu es a high leve l of
s ig n.al on BAK in r es pon se to it. The CPU k ee ps address bus (ADO - ADl5). data bus
(00.-07) . MEO . ME I. R/ W. and OD high impedan ce wh en BAK is in hi gh le ve l.
@ OPF
O per at ion C« ><.l e fetch sig nal \ \l hich is se nt out \vh en CP lJ fetc hes operation C <><ic
(insll'uc ti on code).
0 l'F is iss ued only wh en op er a1 ion co de is fow h cd n nd will not be i ss ued in fcwh i ng
addr ess data. i n1m edi a1 e data. a nd sec ond by 1e of the \\VO- ste p in s tr uct i on .
4> 0 $
A~Ao t s _ ____ ~X~ ------- -~L
M EO
OPF
@ INO-IN7
-,---------.
I I
~-~ -~
-
Las i
I Cye ie
_ ,,_ __ Ope r at i on cooe _ _ __,
toteh
Inp ut p ort through \Vhich the C l)\ J n:c-:i vt s 8- hi1 dat a i nt< ) the accu n1u lat or . . ;\ s i nt erna l
pu ll up re sist or is us ed . the CPU assum es it to be high le ve l when n.ol co nn ec ted.
@ p<P
External latch clock. With high l eve l of this cl ock. the conten ts of li te <1ccumu lator is
sent on the data bus. Addition of IC will co mp r ise an outpul port.
REFERENCE: ATP in structio n.
@PU , PV
Th c:sc arc CPU internal nipflo1> outputs. PU and PV arc furnish ed w ilh se l and reset
in s1r uci ions.
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