Sharp CE-150 - Page 254

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@ WA IT
CJ> U wait signal. A high on this line stops the clock '1> so that the CPU halts it>
operation. 1 \s soo n "' WA IT turns lo", the Cl' U rcM1mcs the operation.
Rt1s ic CIOCk 4>0$ / \'- _ __, /
\'-- ___, / \ '--__, / \ '-- ___,/
\
Clock
~ I
\~--'I
\ ._ _ _____ .....JI
\
\'lAIT
'-- --- ---- -- ---- -- ----- - --- - --~-~
NOTE. WA is th~ Jlipllopdedi<:aled to WA IT. by which the WAIT input is received a1 the talhng
edge or the ctock 4> 0$ Because the CPU operating cloc k 4> stops when WA is hogh. 11
makes the CPU
0
stoppe<j. consequently.
@ HO - H7
I.CD b ackphll c sign;il o ut p uc. As the li quid cry stal tfa play (lC f>l is d ri,c n by
ba ckplate s ig nals an d scg 1n cnt si gna1s. the ( ' l> U co ntrols the ba ckplate sign ;, d s.
@ VA , VB , VM, VDIS
I .CD bac kp l at e pow er s 11 pply inp1 11 s.
@ HIN
I npu t signal 10 the counter from which tl tc LCD backplalc signal;, M0 - 117 arc
generated. 1'om1all}. connected 10 pin llA or th e CPU .
@ HA
CPU internal divid er ou tp ut pin. It is used for the ba;ic clock that dri ve, the LCD t hat
ctl nncctcd \ Yi ch tll!\
1
a nd the s.cg n1tnt signal gcncrating l .S J.
@ DI SP
l. (' f) on/off control l\ig nal output \v hi ch ca 1l be se t or re set by n1 c an s <lf instru ct ion.
@ BFO, BFI
BF nipOop output ( llF O) and i nput (B FI). The H I' OipOop is rc "Sc t bi• the OFF
instruction from the CPU. and "ill be set when the input 13FI is turned to high level.
ll FO is in low level when the BF OipOop is se t and in hi gh level when R'.SCI.
As VG G is power su pply to the BF OipOop. the conle n t' or the OipOop are retained as
lo
11 g as VGG is in supp ly.
No rrna ll y. it is u ~cd for rn c n1 ory back up sy stcn1 .
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