Sharp CE-150 - Page 258

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2-3-2. Interrupts
·nicrc ar e follow ing t hr ee k ind ~ of inte rr upt for th e LH5801 CPU.
0 Non-maskable interrupt
W he n i\ MI is turned fr om l ow to high leve l. it sets the flipflop I RO active. upon wh ich
tim e imcrrupt is req ue s ted to the CP U. so that the CPU star ts executing the interrupt
processing after co n1pl ct io n of c ur rent in s1ructi( >fl executi on .
Si n ce the non- rna sk ah lc int.:rrt 1pt is gi ve n \Vi th the highest pr io ri ty t> r dcr . c11 e i nt e rr upt
wi ll be ackno wl ed ge d at on ce. regardless of its internal state.
IRO 'v iii be re se t in a c( n1rst· of the interrupt process.
As the NIM input is sampled by t he clock <PH. it wi ll be come 250k Hnv he n thc4M H7
cfy~ t a l os ci llator i~ co nn ec te d.
<PH
CP U i ntern.a l
XLO
d Os c ll lat o1
XLI
S•;n c h1 on iLi 11 g- - -'
pu :S c
mo --- - --"
I T) S ll UC I JOn exe cu te
ln t <,: rJu pt
t'c k n riwlo:."ft;~r:
<P H
lntertvpl processing
/' Reset I RO
\Vhcn j\1 1\. · 11 is turned h ig h. the (:F 'U cr eates synchronizing pu lse at the ri si ng ed ge of th e
c lo ck <l>H , whic h se ts IR O acti ve . If IRO is active when the CPU ackno wl.: dged th e
inc crr upt after co111p lc ti< n1 <> f executio n. it g t )C'-S in to the int er ru pt ro uti ne an<l I RO is re se t in
a cour ::;c <>f the interrupt proc ess i ng.
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