A
ll
and more about Sharp PC-1500
at
http://www.PC-1500.info
Q) Ti
mer
interrupt
When interrupt
i'
rcquc.1cd from the timer.
it
sc1s
1he
OipOop
IRI
ac1h
c. If
1hc
interrupt enable IE
i,
aeti\e al
1hi>
poinl.
1he
CPU
stan> executing the mtcrrup1
processing after
conlplc1ic1n
t>(
current
in~truction
cxttuti<>n. and IR I
''ill
be
reset in
a course
of
the interrupt
prcH:c:-.."'
.
\\
,.
ht:
n
in
te
rr
upt
i!!i
requested
\\flilc
IF
i~
inacti\'c, the lntcrrupt
\\'ill
he.:
ignored
C\Crl
1hough
IR
I
is
set.
Timer interrupt processing
se
qu
ence
Return
to
main routine
I • $
~
·
-
~
0 •
I(
0 •• ,
.... . $
~
I •$
f
li
• $
5 I •$
1rr•11
... H
"f
l»•
· · l
'l
"fl1e
l
~TI
instruction
is
u~d
for
ret
urning
lr<nn
thc int
C'rrup
t
procc
s~i
ng
r
ou1i11..:
to
1hc
n1ain
r<>utine.
lk."(<:'u~
the
content~
of
the T rcgi,tcr and the progrJOl counter
;.ire
st<1rc<l
in the
'ta
ck
at
the
beginning
of
the interrupt
prOCC>sing
routine. the contents
of
the T register in the stack
n:tums by the RTt instruction. Sin
<-.:
the interrupt
enable
ll;ig IE
i,
con1ained in the T
rcgis1cr
.
1he
contcnl> ol
IF.
irnmcdiatcly octore the in1ernipt return>
b)
the RTI
i
n
~
t
ruction.
To
disable
1na
skc.
1bl..:-
or
tinter i
nt
c1
rup1
b)
the
n1ai
n rouli
nc
af
t
er
returning triun the
interr
up
t process
in
g
r<n
1t
inc.
1h
i.;
bi l in
1h
...:
:i
la
<.:k
corresponding to the
tla
g IE
n1u~t
be l'C'\l:t.
Priority
order
of
interrupts
( I) Non-maskable
i111
or
r11
p1 rc,
p<>r
lC
I>
to
th('
int
errupt
r..::qul·~
t
\\h.-tl
C\Cr
the
Cl)
U
in1ern;.1l
s1:uc
nta~
be
.
,
\l
so.
it
n.-sponds
in tl.e
fi()t
pri<>rit~
e'en
durin.g c,,ccution
of
interrupt
routine
by
c>1hcr
in1crrupt.
-··
·
-·
i
~..........,
-....-
~·
·
'
l~
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not sale this PDF !!!
..
·~-
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...
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