DV-600S
DV-600H
11-9. IC507 BR93L46F EEPROM
Terminal Terminal name In/Output Function
2 VCC – Power
7 GND – All input/output reference voltage, 0V
3 CS Input Tip select input
4 CLK Input Sirial clock input
5 DIN Input Start bit, operation code, address and serial data input
6 OCNT Output Serial data output, READY/BUSY internal status indication output
• Block Diagram
C S
S K
D I
D O
Dummy bit
Instruction
register
Data
resistor
R/W
Amp.
Address
buffer
Address
Decoder
Instruction decode control
clock generation
Wave voltage
detection
Write
inhibition
High voltage
generation
bit
EEPROM
Aray
1,024
6bit
6bit
16bit
16bit
1 VDD – Digitan power +3.3V
2 HADR (0) Input CPU Address bus
3 HADR (1) Input CPU Address bus
4 HADR (2) Input CPU Address bus
5 HADR (3) Input CPU Address bus
6 HADR (4) Input CPU Address bus
7 HADR (5) Input CPU Address bus
8 VSS – Digital GND
9 VDD – Digitan power +3.3V
10 HADR (6) Input CPU Address bus
11 HADR (7) Input CPU Address bus
12 HADAT (0) Input CPU Data bus
13 HADAT (1) Input CPU Data bus
14 HADAT (2) Input CPU Data bus
15 HADAT (3) Input CPU Data bus
16 VSS – Digital GND
17 VDD – Digitan power +3.3V
18 HADAT (4) Input CPU Data bus
19 HADAT (5) Input CPU Data bus
20 HADAT (6) Input CPU Data bus
21 HADAT (7) Input CPU Data bus
22 INT Input CPU Data bus
23 WAIT Input CPU Data bus
24 VSS – Digital GND
25 VDD – Digitan power +3.3V
26 HRD Input CPU read signal
27 HWR Input CPU write signal
28 HAS Input CPU address strobe signal
29 HCS Input CPU tip select signal
30 HIM Input CPU bus control selection signal (I/M mode = H/L)
11-10. IC508 IX1516GE GAMMA S-P-TONE
Terminal
Terminal name In/Output Function
11-9
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