HT-DV40H
8 – 20
GPIO/M_DD[16] 172 Input/Output GPIO[47] or SDRAM data bus bit 16
M_CS1_B/GPIO 173 Input/Output SDRAM chip select 1, or GPIO[48]
Symbol Pin # Input/Output Description
Priority selection Function Dir
hw_cfg_chg[5]=1’b1 SDRAM data bus [16] Input/Output
gpio_first[2][15] = 1 GPIO[47] Input/Output
sft_cfg13[8:4] = 5'b01110 ADC_DATA Input
sft_cfg13[11:9] = 3'b100 AT_RESET_B Output
sft_cfg13[14:12] = 3'b001 AT_D[7] Input/Output
sft_cfg13[14:12] = 3'b100 AT_D[7] Input/Output
{sft_cfg20[0],sft_cfg7[5:4]} =
3'b001
656_DATA[7] Output
{sft_cfg20[1],sft_cfg19[5:4]} =
3'b001
HD_DATA[7] Output
{sft_cfg20[2],sft_cfg14[7:6]} =
3'b001
SRGB_DATA[7] Output
sft_cfg11[8:6] = 3'b011 TS_DATA[3] Input/Output
sft_cfg7[11:8] = 4'b0110 VGA_CLK Input
sft_cfg0[13:12] = 1 TV_LCD_B[5] Output
sfg_cfg16[11:8] = 4'b0001 FM_GPIOB[10] Input/Output
sfg_cfg16[15:12] = 4'b0110 FM_GPIOB[13] Input/Output
sfg_cfg17[3:0] = 4'b0101 FM_GPIOB[19] Input/Output
sfg_cfg17[15:12] = 4'b0100 FM_GPIOB[26] Input/Output
sfg_cfg18[3:0] = 4'b1000 FM_GPIOB[35] Input/Output
sfg_cfg18[3:0] = 4'b1001 FM_GPIOB[41] Input/Output
(other) GPIO[47] (default) Input/Output
Priority selection Function Dir
sft_cfg0[7]=1’b1 SDRAM chip select 1 (default) Output
gpio_first[3][0] = 1 GPIO[48] Input/Output
sft_cfg13[8:4] = 5'b01111 ADC_DATA Input
sft_cfg13[11:9] = 3'b100 AT_DMACK_B Output
sft_cfg13[11:9] = 3'b101
AT_INTRQ
Input
sft_cfg13[11:9] = 3'b110 AT_INTRQ Input
sft_cfg13[14:12] = 3'b100 AT_D[8] Input/Output
sft_cfg13[14:12] = 3'b111 AT_D[15] Input/Output
sft_cfg1[8:6] = 3'b100 FL_MEM_CSALL_B Output
{sft_cfg20[0],sft_cfg7[5:4]} =
3'b001
656_CLK Output
{sft_cfg20[1],sft_cfg19[5:4]} =
3'b001
HD_VCLK Input
{sft_cfg20[2],sft_cfg14[7:6]} =
3'b001
SRGB_DCLK Output
sft_cfg7[11:8] = 4'b0111 VGA_CLK Input
sft_cfg0[13:12] = 1 TV_LCD_DVAL Output
sft_cfg0[13:12] = 2 TV_LCD_DVAL Output
sfg_cfg16[7:4] = 4'b0001 FM_GPIOB[9] Input/Output
sfg_cfg17[3:0] = 4'b0100 FM_GPIOB[18] Input/Output
(other) GPIO[48] Input/Output