Sharp HT-DV40H - Page 104

HT-DV40H
8 – 19
GPIO/M_DD[18] 169 Input/Output GPIO[45] or SDRAM data bus bit 18
GPIO/M_DD[17] 171 Input/Output GPIO[46] or SDRAM data bus bit 17
Symbol Pin # Input/Output Description
Priority selection Function Dir
hw_cfg_chg[5]=1’b1 SDRAM data bus [18] Input/Output
gpio_first[2][13] = 1 GPIO[45] Input/Output
sft_cfg13[14:12] = 3'b001 AT_D[6] Input/Output
sft_cfg13[14:12] = 3'b100 AT_D[6] Input/Output
{sft_cfg20[0],sft_cfg7[5:4]} =
3'b001
656_DATA[5] Output
{sft_cfg20[1],sft_cfg19[5:4]} =
3'b001
HD_DATA[5] Output
{sft_cfg20[2],sft_cfg14[7:6]}=
3'b001
SRGB_DATA[5] Output
sft_cfg11[8:6] = 3'b011 TS_DATA[1] Input/Output
sft_cfg0[13:12] = 1 TV_LCD_B[3] Output
sfg_cfg15[15:12] = 4'b0100 FM_GPIOB[7] Input/Output
sfg_cfg16[15:12] = 4'b0001 FM_GPIOB[12] Input/Output
sfg_cfg16[15:12] = 4'b0110 FM_GPIOB[15] Input/Output
sfg_cfg17[3:0] = 4'b0101 FM_GPIOB[17] Input/Output
sfg_cfg18[3:0] = 4'b1000 FM_GPIOB[37] Input/Output
sfg_cfg18[3:0] = 4'b1001 FM_GPIOB[39] Input/Output
(other) GPIO[45] (default) Input/Output
Priority selection Function Dir
hw_cfg_chg[5]=1’b1 SDRAM data bus [17] Input/Output
gpio_first[2][14] = 1 GPIO[46] Input/Output
sft_cfg13[14:12] = 3'b001 AT_D[8] Input/Output
sft_cfg13[14:12] = 3'b100 AT_D[9] Input/Output
{sft_cfg20[0],sft_cfg7[5:4]} =
3'b001
656_DATA[6] Output
{sft_cfg20[1],sft_cfg19[5:4]} =
3'b001
HD_DATA[6] Output
{sft_cfg20[2],sft_cfg14[7:6]}=
3'b001
SRGB_DATA[6] Output
sft_cfg11[8:6] = 3'b011 TS_DATA[2] Input/Output
sft_cfg0[13:12] = 1 TV_LCD_B[4] Output
sfg_cfg16[3:0] = 4'b0100 FM_GPIOB[8] Input/Output
sfg_cfg16[11:8] = 4'b0001 FM_GPIOB[11] Input/Output
sfg_cfg16[15:12] = 4'b0110 FM_GPIOB[14] Input/Output
sfg_cfg17[3:0] = 4'b0101 FM_GPIOB[18] Input/Output
sfg_cfg18[3:0] = 4'b1000 FM_GPIOB[36] Input/Output
sfg_cfg18[3:0] = 4'b1001 FM_GPIOB[40] Input/Output
(other) GPIO[46] (default) Input/Output