Sharp HT-DV40H - Page 115

HT-DV40H
8 – 30
IC4 VHIEM638165-1 : 16 Bit, SDRAM ( EM638165 ) ( 1/2 )
BLOCK DIAGRAM
Figure 8-3 BLOCK DIAGRAM OF IC
CLOCK
BUFFER
COMMAND
DECODER
COLUMN
COUNTER
ADDRESS
BUFFER
MODE
REGISTER
CONTROL
SIGNAL
GENERATOR
Buffer
Column Decoder
1MX16
CELL ARRAY
(BANK #A)
Decoder
REFRESH
COUNTER
CLOCK
CKE
CS#
RAS#
CAS#
WE#
UDQM
LDQM
A0
A11
BA0
BA1
~
DQ0
DQ15
Column Decoder
1MX16
CELL ARRAY
(BANK #B)
Decoder
Column Decoder
1MX16
CELL ARRAY
(BANK #C)
Decoder
Column Decoder
1MX16
CELL ARRAY
(BANK #D)
Decoder