Sharp HT-DV40H - Page 120

HT-DV40H
8 – 35
IC10 VHINJU26220FN : DOLBY VIRTUAL SPEAKER / HEADPHONE DECODER ( NJU26220FN ) ( 1/3 )
BLOCK DIAGRAM
Figure 8-5 BLOCK DIAGRAM OF IC
HPVCC1 66 Power HDMI PLL1 power 3.3V
HPVCC2 81 Power HDMI PLL2 power 3.3V
TMDSVCC18 84 Power HDMI analog power 1.8V
AVDD1 102 Power Video DAC power 3.3V
AVSS1 98 Gnd Video DAC GND
AVDD2 95 Power Video DAC power 3.3V
AVSS2 94 Gnd Video DAC GND
SPLLVCC 127 Power System PLL power 1.8V
SPLLGND 1 Gnd System PLL GND
External RC Pins
EXT_SWING 67 LVTTL Output HDMI Voltage Swing Adjust Resistor
SPLLRC 128 LVTTL Output System PLL Low Pass Filter
DAC_VBSP 99 LVTTL Output Connect a capacitor to AVDD1
DAC_FSADJ 100 LVTTL Output Connect a Reference Voltage Adjust Resistor to AVSS1
DAC_REFOUT 101 LVTTL Output Connect a capacitor to AVDD1
Mnemonic Pin# Type Dir. Description
NJU26220
AD1/SDIN
SCL/SCK
SERIAL
HOST
INTERFACE
24bit Fixed-point DSP Core
SERIAL AUDIO
INTERFACE
24-BIT x 24-BIT
MULTIPLIER
ADDRESS GENERATION UNIT
PROGRAM
CONTROL
ALU
SDA/SDOUT
RESETb
MCK
TIMING
GENERATOR
/ PLL
DATA
RAM
FIRMWARE
ROM
General I/O
INTERFACE
PROC
MUTEb
SEL
WDC
BCK0
LR0
SDO0
SDI*
SD01
SD02
BCKI
SD03
LRI
CLK
CLKOUT
AD2/SSb
Monitor
L/R
C/SW
SL/SR