Sharp HT-DV40H - Page 98

HT-DV40H
8 – 13
M_A[6] 139 Input/Output SDRAM address bus [6]
M_A[5] 140 Input/Output SDRAM address bus [5]
M_A[4] 142 Input/Output SDRAM address bus [4]
M_DQM1/GPIO 143 Input/Output SDRAM data input/output mask for M_DD[15:8], or GPIOA[27]
M_DQM0/GPIO 144 Input/Output SDRAM data input/output mask for M_DD[7:0] or GPIOA[28]
M_BA1/GPIO 145 Input/Output SDRAM bank select address [1] or GPIOA[29]
M_A[10] 146 Output SDRAM address bus [10]
M_A[0] 147 Output SDRAM address bus [0]
M_A[1] 149 Output SDRAM address bus [1]
M_A[2] 150 Output SDRAM address bus [2]
M_A[3] 151 Output SDRAM address bus [3]
GPIO/M_DD[31] 152 Input/Output SDRAM data bus bit 31 or GPIO[30]
GPIO/M_DD[30] 153 Input/Output SDRAM data bus bit 30 or GPIO[31]
Symbol Pin # Input/Output Description
Priority selection Function Dir
sft_cfg0[3]=1íb1
SDRAM data input/output
mask for M_DD[15:8] (default)
Input/Output
(other) GPIO[27]
Input/Output
Priority selection Function Dir
sft_cfg0[2]=1íb1
SDRAM data input/output
mask for M_DD[7:0] (default)
Input/Output
(other) GPIO[28]
Input/Output
Priority selection Function Dir
sft_cfg0[6]=1íb1
SDRAM bank select address
[1] (default)
Input/Output
sft_cfg13[3:0] = 4'b1010 IEC_RX
Input
sft_cfg13[8:4] = 5'b01011 ADC_DATA
Input
{sft_cfg20[5:3],sft_cfg14[1
5:13]} = 6'b010000
INT0_7
Input
(other) GPIO[29]
Input/Output
Priority selection Function Dir
hw_cfg_chg[5]=1íb1 SDRAM data bus [31]
Input/Output
gpio_first[1][14] = 1 GPIO[30]
Input/Output
hw_cfg_chg[4] = 1'b1 FL_ROM_DATA[15]
Input/Output
sft_cfg13[11:9] = 3'b100 AT_DIOW_B
Output
sft_cfg13[14:12] = 3'b001 AT_D[15]
Input/Output
{sft_cfg20[5:3],sft_cfg14[1
5:13]} = 6'b001000
INT0_7
Input
sft_cfg0[13:12] = 1 TV_LCD_R[0]
Output
sfg_cfg15[5:3] = 3'b101 FM_GPIOB[4]
Input/Output
sfg_cfg17[11:8] = 4'b0100 FM_GPIOB[21]
Input/Output
sfg_cfg17[15:12] = 4'b1011 FM_GPIOB[26]
Input/Output
sfg_cfg18[3:0] = 4'b0001 FM_GPIOB[27]
Input/Output
(other) GPIO[30] (default)
Input/Output
Priority selection Function Dir
hw_cfg_chg[5]=1íb1 SDRAM data bus [30]
Input/Output
gpio_first[1][15] = 1 GPIO[31]
Input/Output
hw_cfg_chg[4] = 1'b1 FL_ROM_DATA[14]
Input/Output
sft_cfg13[14:12] = 3'b001 AT_D[0]
Input/Output
sft_cfg13[14:12] = 3'b100 AT_D[0]
Input/Output
sft_cfg0[13:12] = 1 TV_LCD_R[1]
Output
sfg_cfg15[2:0] = 3'b100 FM_GPIOB[0]
Input/Output
sfg_cfg15[8:6] = 3'b101 FM_GPIOB[5]
Input/Output
sfg_cfg17[15:12] =4'b0001 FM_GPIOB[26]
Input/Output
sfg_cfg18[3:0] = 4'b1001 FM_GPIOB[27]
Input/Output
(other) GPIO[31] (default)
Input/Output