Sharp IQ-9200

2-7. EEPROM (uPD28C64GX) -
1) Functional description
The »PD28C64GX has the following two functions.
The end of the data cycle can be
exactly known from the external
source, and it may also shorten the
write time.
* Data poll function
It has three modes to kill noise, to
detect the Vcc power supply level,
and the write prohibit logic.
*’ Write error prevent function
@ Data.poll function
With the data poll function, the exact end point of the write cycle
can be confirmed software-wise. Using this function, the control
can move to a next write cycle immediately after the present write
cycle has ended.
The maximum value of the pPD28C64GxX write cycle time is set to
12ms, while the standard value at the end of:the write cycle is
7ms. So, the write time can be reduced if this data poll function is
utilized.
‘Do the following procedure to poll data.
(a) After writing the data in the uPD28C64GX with the WE con-
trol write signal, the signal WE is retained high level and the
data in the written address (in the page write mode, the last
; written address) is read (refer to the read mode timing).
(b) The output data is compared with the written data.
- If /O7 of the. output data is verified successfully with the
written data, the write operation is finished. Now, you can
proceed to a next write cycle. If the write was not completed,
- the inversion of the write data are sent and "0" is sent to all
bits through 1/00~1/O6.
NOTE: Refer to the 2-operation mode for the WE control write
mode and the page write mode.
Example) If the write data was "10101010," the output data will
be "10101010" when the write has been completed. If
not completed, the output data will be "00000000".
Last data write ” Write completion
) a cas |
‘CE
(input)
PRIN
EN
GE
(input)
=
Ne
Ser
WE (input)
VO7. cS ee) Swerigr (Output) (Output) - (Output)
i ad a eoie "yb seb sry a as Lyon l fei
A0~A14
(input/output) —
NOTE: The broken liné represents an high impedance state. +n” represents an address-n.
@® Write error prevention function
The pPD28C64GX has the following three. modes to prevent data
- _ Write error, a,
sgh (a): ‘Noise. pesventon: Sorgen
es). .Write.is prohibited if the WE pulse i is cinder 15ns.
by
Supply voltage Vcc level detect function
Write i is Prohibited if the power supply voltage is under 2.5V.
Rete _ Write prohibit logic .- “
Write is: prohibited if OE="VIL" OF. . WE="VIH", or CE="VIH",
when the supply. atege! is on or.off..
Od
0Z-9600.11
IQ-9200
2) Block diagram
: Data input/output ~
vce
O———>
VO0~1/07
GND O-——>
Write enable
Output enable
; Chip enable
Y-decoder =>
/O buffer data latch
Y-selection
256K-bit ©
X-decoder.
. memory cell array
Address buffer address latch
Fig.11 »PD28C64GX block diagram
' 3) Pin layout
~45—
1
2
3
4
5
6
7
8
pPD28C64GX
vO7
A10 0
Fig.12 pPD28C64GxX pin layout
4) Pin description
ce — —ceeonige =
FOE | Output enable input =|
WE | Wit enabie put
Vcc Powersupply
fend
Inc
Not connected
5) Operation mode
The PD28C64GX has five operation modes. For all modes, set -CE,
-OE-, and -WE to the voltage level shown in Table 2-1. The
pPD28C64GxX, however, leaves the factory with all bits "1" canceled.
/00~V/07
Data output
Seb X | High impedance
Vi [Vit [Data input
VIHH | VIL . |Data input (DIH=VIH)
vie |
ip erase | viL_|
Ed
Ex
NOTE:
VIH: High level input voltage
VIHH: +15V0.5V
VIL: low level input voltage
X: VIL or VIH
Table 2-1. Operation modes