Sharp IQ-9200

® @
esr es Slash os te A
pe re ee ee ae
Tera, el
LeDon Voltage boosting Voltage decreasing
®@®@®@eod
VEE
I
LCD off
x Although the voltage VCC-VF is added to VEE while the unit is off,
no voltage is added to the LCD driver since it is turned off within
LVC (transistor switched).
5. Operation of the transparent tablet
(A/D converter)
To locate the point on the transparent tablet, it uses a tablet control
transistor, an A/D converter, and a gate array.
In the A/D converter, the coordinates X and Y of the tablet is con-
verted from the analog voltage to a 10-bit data. (Conversion is done
after checking the pressure level is above a fixed level.) The tablet is
multiplexed via the control transistor, and voltage is added towards X
and Y axis. A voltage proportionate to the pressed point is sent to YL
for the X-axis and XL for the Y-axis. The gate array controls the A/D
converter (read/write) and output of the transistor.
To save power consumption, the A/D converter is kept in the standby
mode (CS and WR forcing low) and the reference voltage for the A/D
converter is supplied only when required (SWAN signal).
(Atotl (Aton) Pressure on tablet
: Pressure Coordinate
x
Pressure
ony.
Coordinate
X gon X
MON
ADCSN J ] I T T T l
‘¢— Pressure on tablet
SWAN
| J
VIN4
.TC35083F
Ice
22222227771
ASSN
C2272 22 eZ
1Z93G33
1c2
~1{7-
OZ-9600 11
1Q-9200.
6. LCD contrast adjustment. -
Contrast
adjustment
using
electronic
potentiometer
is
controlled
in
the
following
manner.
CPU
data
are
latched
in
the
common
driver
(8-bit
contrast
adjust
parameter)
and
sent
out.
These
outputs
are
sent
to
LVC
(SC3611)
where
the
LCD
voltages
appropriate
to
the
data
are
sent
through
V1iV6.
VEE
From the voltage circuit
Data bus V6 (V1 X 12/13)
V3 (V4. X 14/43)
V4 (V1 X 2/13)
V5 (V1 X 4/13)
Address bus
$C3611
Lvc
LH5806AM
CPU
Common driver
VR2VR8
are
issued
as
a
7-bit
data
of
LSB
through
MSB.
When
the
data are at the highest value, the output voltage is the largest.
Source
voltage
for
V1V6
is
from
VEE
that
supplied
from
the
booster
circuit.
Meanwhile,
ON
and
OFF
of
V1V6
outputs
are
controlled
by
the
EEO
line
of
the
CPU.
When EE0 is at a high, the output voltage is active. When EE0 is at a
low, the output voltage is not active.
7. Low battery detection
The main battery level is monitored in two stages. When a low battery
is
sensed
first,
the
BATT.
indicator
is
turned
on
(caution
level).
If
a
further drop is found, it turns off (fatal level).
[t
also
monitors
the
backup
battery
and
the
RAM
card
data
protection
battery
voltage.
;
:
@ Operating theory
Main battery
Backup battery (main)
Data protect battery (card)
(LH5806) (LZ93G33) i
Data address bus
(SMC5245)
The
low
battery
function
is
incorporated
in
RTC
(SMC5245),
the
detection
level
and
the
detection
line
are
switched
by
software.
When
a
low
battery
is
found
by
RTC,
a
high
state
of
signal
is
issued
onto
the
ALARMS
line
to
inform
the
occurrence
to
the
CPU.
,
@ Main battery detection :
Software switch is done using the VO'line of RTC to select a
two-stage detect level. The input is at 1.5~2.5M when the caution
level is discovered.
@® Backup battery detection
The internal switch is selected on VD1 and VD2 lines of RTC, and
a single internal detector is used to detect.