Sharp MD-E9000H - Page 81

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MD-E9000H
FunctionTerminal Name Input/Output
Pin No.
ICT21 VHiLC72723/-1: RDS Decorder (LC72723)
Figure 81 BLOCK DIAGRAM OF IC
1 VREF Output Reference voltage output. (Vdda/2)
2 MPXIN Input Baseband (multiplexed) signal input.
3 VDDA Input Analog power supply. (+5 V)
4 VSSA — Analog ground.
5 FLOUT Output Subcarrier output. (filter output)
6 CIN Input Subcarrier input. (comparator input)
7 TEST Input Test input.
8 XOUT Output Crystal oscillator output. (4.332 MHz)
9 XIN Input Crystal oscillator input. (external reference signal input)
10 VSSD — Digital ground.
11 VDDD Input Digital power supply. (+5 V)
12 MODE Input Read mode setting. (0: master, 1: slave)
13 RST Input RDS-ID/RAM reset. (positive polarity)
14 RDDA Output RDS data output.
15 RDCL Input/Output RDS clock output. (master mode)
RDS clock input. (slave mode)
16 RDS-ID/READY Output RDS-ID/READY output. (negative polarity)
3
4
REFERENCE
VOLTAGE
VDDA
VSSA
2
MPXIN
7
TEST
9
XIN
1
VREF
5
FLOUT
6
CIN
8
XOUT
ANTIALIASING
FILTER
TEST
OSC
CLK (4.332 MHz)
57 kHz
BPF
(SCF)
SMOOTHING
FILTER
VREF
–
+
PLL
(57 kHz)
CLOCK
RECOVERY
(1187.5 Hz)
DATA
DECODER
RAM
(128-bits)
RDS ID
DETECT
11
VDDD
10
VSSD
14
RDDA
15
RDCL
12
MODE
13
RST
16
RDS-ID/
READY
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RDS-ID/READY
RDCL
RDDA
RST
MODE
VDDD
VSSD
XIN
XOUT
TEST
CIN
FLOUT
VSSA
VDDA
MPXIN
VREF