Sharp MZ-5600 - Page 62

(4) VDC1 (SP6102-035)
VDC1 functional outline
* Produces the DCK (dot clock) by halving 3 master
r clocks for 400 rasters (CKO), 200 rasters (CK1) and
I ,- superimposing (CK2). The 2XCCK (GDC clock) is
produced by dividing the above master clocks by 16.
i •
! Generates the RASO-RAS5, CAS, and bidirectional
I buffer gate signals VDEO-VDE2, which are used by the
CPU or GDC to access the VRAM.
• Produces display timing control signals.
L VD~1 !timing control) block diagram
;RESET·
.,
, Vcc
,
~;
GNO
00
01
02
CS
..
•
•
r p r r r r
latm
r---
f-<
0::
0
0-
0
"-
-
"--~
r-
---
CKO
CKl
CK2
42.95MHz
28.64'H, CLOCK 'r CLOCK I----->
SELECT DIVIDE
r
<:
>
-
I
latch
l
DCK 2xCCLK CPUA
r
v. ~
t t
WE DBD
.....
L.....--.
DECODE
MPXER
DECOffi
.
f--
i
TIMING GENERATION
LOAD OE RCS CRL S /L READY RAS
GDE
Fig. 74
-61-
-
MZ-5600
-
-
-
-
-
RASO
RASl
RAS2
RAS3
RAS4
RAS5
VDEO
VDEl
VDE2
CAS
"i5TSP
BLANK
HSYNC
DBIN