Sharp UP-3300 - Page 53

3) Terminal Name and Description (MB62H149)
Fig. 7
Pin
No.
Terminal
name
Host/
Sub
In/
Out
Description
1 CLK Sub In Clock in (16 MHz)
2 — — — N.U.
3 IORQ Sub In I/O request
4 MREQ Sub In Memory request
5 RDS Sub In Read from sub
6 WRS Sub In Write from sub
7 INTS Sub Out Interrupt to sub
8 φ Sub Out Clock out
9 TM0 Sub In Timer 0
10 TM1 Sub Out Timer 1
11 MRD Sub Out Memory read
12 VSS — — GND
13 WAIT Sub Out Wait signal
14 A15 Sub Out Address bus for DMA
16 A9 Sub Out
17 A8 Sub Out
18 A5 Sub In
19 A4 Sub In
20 A1 Sub In
21 A0 Sub In
22 DAK01 Sub In DMA acknowledge 0+1
23 — — — N.U.
24 MWR0 Sub Out Memory write
25 D7 Sub I/O Data bus
26 D6 Sub I/O
27 D5 Sub I/O
28 D4 Sub I/O
29 D3 Sub I/O
30 D2 Sub I/O
31 D1 Sub I/O
32 D0 Sub I/O
33 VDD — — +5V
34 — — — N.U.
35 RES Host In Reset
Pin
No.
Terminal
name
Host/
Sub
In/
Out
Description
36 IO/WR Sub I/O I/O write
37 IO/RD Sub I/O I/O read
38 AEN Sub In Address enable from DMAC
39 AST Sub In Address strobe from DMAC
40 TCS Sub In Terminal count
41 DAK23 Sub In DMA acknowledge 2+3
42 DRQRS Sub Out DMA request read to sub
43 DRQWS Sub Out DMA request write to sub
44 RDH Host In Read from Host
45 WRH Host In write from Host
46 INTH Host Out Interrupt to host
47 DAK Host In DMA acknowledge from host
48 TCH Host In Terminal count from host
49 DRQWH Host Out DMA request read to host
50 DRQWH Host Out DMA request write to host
51 CS Host In Chip select from host
52 VSS — — GND
53 — — — N.U.
54 DB0 Host I/O Data bus
55 DB1 Host I/O Data bus
56 DB2 Host I/O Data bus
57 DB3 Host I/O Data bus
58 DB4 Host I/O Data bus
59 DB5 Host I/O Data bus
60 DB6 Host I/O Data bus
61 DB7 Host I/O Data bus
62 AB0 Host In Address bus from host
63 — — — N.U.
64 AB1 Host In Address bus from host
65 COL Sub In Collision detect signal
66 RDI Sub In Receive data from receiver
67 TDI Sub Out Transmmit data to driver
68 RTS Sub In Request to send
69 RXC Sub Out Receive clock to ADLC
70 RXD Sub Out Receive data to ADLC
71 TXC Sub Out Transmmit clock
72 TXD Sub In Transmmit data
73 VDD — — +5V
74 E Sub In Enable clock to ADLC
75 IRQ Sub In Interrupt request from ADLC
76 LCS Sub Out Link controller chip select
77 — — — N.U.
78 RS1 Sub Out Register select 1
79 RS0 Sub Out Register select 0
80 MSK Sub Out Mask signal
14
17.9 ±
0.4
20
23.9 ±
0.6
0.8 ±
0.15
0.35 ±
0.1
INDEX
LEAD
NO
1
24
25
40
41
64
65
80
7 – 17